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1. 发明授权

US06350627B1 Interlevel dielectric thickness monitor for complex semiconductor chips 有权
标题翻译：复合半导体芯片的层间电介质厚度监测器
公开(公告)号：US06350627B1
公开(公告)日：2002-02-26
申请号：US09548741
申请日：2000-04-13
申请人： Tho Le La , John Jianshi Wang , Hao Fang
发明人： Tho Le La , John Jianshi Wang , Hao Fang
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/76801 , H01L22/12
摘要： A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box. Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.
摘要翻译：一种在半导体芯片内测量不同类型的多个结构之上的电介质层的厚度的方法。该方法包括以下步骤：在半导体芯片上形成多个监视盒，使得所述多个监视盒中的每一个表示半导体芯片内的结构类型，并具有与多种不同结构类型之一基本相同的台阶高度 ; 在所述半导体芯片上形成介电层; 以及测量所述多个监视盒中的至少一个的所述电介质层的厚度，其中所述厚度表示所述电介质层的厚度，所述电介质层的厚度在由所述监视盒所表示的结构类型的结构之上。还公开了允许用于精确的电介质厚度测量。芯片包括：位于半导体芯片内的表面上的不同类型的多个结构; 以及位于半导体芯片内的所述表面上的多个监视器盒，可以在其上进行介电厚度的测量，其中多个监视盒中的每一个表示半导体芯片内的结构类型。

2. 发明授权

US06072191A Interlevel dielectric thickness monitor for complex semiconductor chips 失效
标题翻译：复合半导体芯片的层间电介质厚度监测器
公开(公告)号：US06072191A
公开(公告)日：2000-06-06
申请号：US991299
申请日：1997-12-16
申请人： Tho Le La , John Jianshi Wang , Hao Fang
发明人： Tho Le La , John Jianshi Wang , Hao Fang
IPC分类号： H01L21/66 , H01L21/768 , H01L23/544 , H01L23/58 , H01L21/4763
CPC分类号： H01L22/34 , H01L21/76801 , H01L22/12
摘要： A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box.Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.
摘要翻译：一种在半导体芯片内测量不同类型的多个结构之上的电介质层的厚度的方法。该方法包括以下步骤：在半导体芯片上形成多个监视盒，使得所述多个监视盒中的每一个表示半导体芯片内的结构类型，并具有与多种不同结构类型之一基本相同的台阶高度 ; 在所述半导体芯片上形成介电层; 以及测量所述多个监视盒中的至少一个上的所述电介质层的厚度，其中所述厚度表示所述电介质层的厚度，所述电介质层在由所述监视盒所表示的结构类型的结构之上。还公开了允许精确的电介质厚度测量的半导体芯片。芯片包括：位于半导体芯片内的表面上的不同类型的多个结构; 以及位于半导体芯片内的所述表面上的多个监视器盒，可以在其上进行介电厚度的测量，其中多个监视盒中的每一个表示半导体芯片内的结构类型。

3. 发明授权

US06312991B1 Elimination of poly cap easy poly 1 contact for NAND product 有权
标题翻译：消除聚碳酸酯容易聚1接触的NAND产品
公开(公告)号：US06312991B1
公开(公告)日：2001-11-06
申请号：US09531582
申请日：2000-03-21
申请人： John Jianshi Wang , Hao Fang , Masaaki Higashitani
发明人： John Jianshi Wang , Hao Fang , Masaaki Higashitani
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107). A second insulating layer (140) is formed over both the select gate transistor region (105) and the memory cell region (111) and first and second contact openings are formed in the second insulating layer (140) down to the gate structure (107) and the control gate region, wherein a depth (X) through the second insulating layer (140) down to the gate structure (107) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.
摘要翻译：形成NAND型快闪存储器件的方法（200）包括以下步骤：在衬底（102）上形成氧化物层（202），并在氧化物层上形成第一导电层（106）。蚀刻第一导电层（106）以在存储单元区域（111）中的选择栅极晶体管区域（105）和浮动栅极结构（106a，106b）中形成栅极结构（107）。然后在存储单元区域（111）之上形成第一绝缘层（110），并且在第一绝缘层（110）之上形成第二导电层（112,118）。在存储单元区域（111）中对字线（122）进行构图以形成控制栅极区域，并且在邻近字线的区域（102,132）中形成在衬底（102）中的源极和漏极区域（130,132） 122）并且在与栅极结构（107）相邻的区域中。在选择栅极晶体管区域（105）和存储单元区域（111）上形成第二绝缘层（140），并且在第二绝缘层（140）中形成第一和第二接触开口至栅极结构（107））和控制栅极区域，其中通过第二绝缘层（140）到达栅极结构（107）并且向下到控制栅极区域的深度（X）大致相同，从而消除了栅极结构的实质上的过蚀刻接触开口

4. 发明授权

US06211058B1 Semiconductor device with multiple contact sizes 有权
标题翻译：具有多种接触尺寸的半导体器件
公开(公告)号：US06211058B1
公开(公告)日：2001-04-03
申请号：US09353781
申请日：1999-07-15
申请人： John Jianshi Wang , Hao Fang
发明人： John Jianshi Wang , Hao Fang
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L23/5226 , H01L2924/0002 , Y10S438/911 , H01L2924/00
摘要： A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simply the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material to the etching process. Where a deep etch is required, a larger contact is used. A shallower etch through similar material uses a smaller contact to slow the etching process. As a result, the etches can complete at about the same time. The technique can be employed to etch any number of contacts. An intermediate size contact can be used where the material to be etched results in a slower etching process. A plurality of contact sizes can be used depending on the depths of etching required and the characteristics material to be etched, so that the etching for all the contacts completes at substantially the same time.
摘要翻译：具有多层的半导体器件按顺序在不同的层上使用不同尺寸的触点，以便简单地制造工艺和所需的蚀刻深度。触点尺寸是根据材料对蚀刻工艺的响应性来选择的。在需要深刻蚀时，使用较大的接触。通过类似材料的较浅蚀刻使用更小的接触来减缓蚀刻工艺。因此，蚀刻可以在大约相同的时间完成。该技术可用于蚀刻任何数量的触点。可以使用中等尺寸的接触件，其中待蚀刻的材料导致较慢的蚀刻工艺。可以根据所需的蚀刻深度和要蚀刻的特征材料使用多个接触尺寸，使得所有触点的蚀刻基本上同时完成。

5. 发明授权

US5994780A Semiconductor device with multiple contact sizes 失效
标题翻译：具有多种接触尺寸的半导体器件
公开(公告)号：US5994780A
公开(公告)日：1999-11-30
申请号：US991052
申请日：1997-12-16
申请人： John Jianshi Wang , Hao Fang
发明人： John Jianshi Wang , Hao Fang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76816 , H01L23/5226 , H01L2924/0002 , Y10S438/911
摘要： A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simplify the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material to the etching process. Where a deep etch is required, a larger contact is used. A shallower etch through similar material uses a smaller contact to slow the etching process. As a result, the etches can complete at about the same time. The technique can be employed to etch any number of contacts. An intermediate size contact can be used where the material to be etched results in a slower etching process. A plurality of contact sizes can be used depending on the depths of etching required and the characteristics of material to be etched, so that the etching for all the contacts completes at substantially the same time.
摘要翻译：具有多个层的半导体器件按顺序在不同层上使用不同尺寸的触点，以简化制造工艺和所需的蚀刻深度。触点尺寸是根据材料对蚀刻工艺的响应性来选择的。在需要深刻蚀时，使用较大的接触。通过类似材料的较浅蚀刻使用更小的接触来减缓蚀刻工艺。因此，蚀刻可以在大约相同的时间完成。该技术可用于蚀刻任何数量的触点。可以使用中等尺寸的接触件，其中待蚀刻的材料导致较慢的蚀刻工艺。可以根据所需的蚀刻深度和要蚀刻的材料的特性来使用多个接触尺寸，使得所有触点的蚀刻基本上同时完成。

6. 发明授权

US06445051B1 Method and system for providing contacts with greater tolerance for misalignment in a flash memory 有权
标题翻译：用于提供触点的方法和系统，其具有对于闪存中未对准的更大容限
公开(公告)号：US06445051B1
公开(公告)日：2002-09-03
申请号：US09563797
申请日：2000-05-02
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/28273
摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.
摘要翻译：公开了一种用于在闪速存储器件中提供多个触点的方法和系统。闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。该方法和系统还包括蚀刻绝缘层以提供多个接触孔。绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤不会蚀刻穿过多个场绝缘区域。该方法和系统还包括用导体填充多个接触孔。

7. 发明授权

US06420240B1 Method for reducing the step height of shallow trench isolation structures 有权
标题翻译：降低浅沟槽隔离结构台阶高度的方法
公开(公告)号：US06420240B1
公开(公告)日：2002-07-16
申请号：US09611701
申请日：2000-07-08
申请人： Wenge Yang , John Jianshi Wang , Hao Fang
发明人： Wenge Yang , John Jianshi Wang , Hao Fang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b) forming the trench, (c) filling the trench with a dielectric material, (d) planarizing the dielectric material,(e) replacing the hard mask with a resist mask, (f) etching back the dielectric material to reduce its step height, and (g) removing the resist mask. In another embodiment, the hard mask used to define the trench is used during the etch back of the dielectric material. In another embodiment, the hard mask used to define the trench is partially stripped before the dielectric material is planarized to reduce its step height.
摘要翻译：在一个实施例中，用于降低浅沟槽隔离结构的台阶高度的方法包括以下动作：（a）在半导体衬底上形成硬掩模以限定沟槽，（b）形成沟槽，（c）用电介质材料，（d）使介电材料平坦化，（e）用抗蚀剂掩模代替硬掩模，（f）蚀刻电介质材料以降低其台阶高度，和（g）去除抗蚀剂掩模。在另一个实施例中，用于限定沟槽的硬掩模在电介质材料的回蚀刻期间使用。在另一个实施例中，用于限定沟槽的硬掩模在电介质材料平坦化之前被部分剥离以降低其台阶高度。

8. 发明授权

US06362049B1 High yield performance semiconductor process flow for NAND flash memory products 有权
标题翻译： NAND闪存产品的高产率性能半导体工艺流程
公开(公告)号：US06362049B1
公开(公告)日：2002-03-26
申请号：US09435213
申请日：1999-11-05
申请人： Salvatore F. Cagnina , Hao Fang , John Jianshi Wang , Kent Kuohua Chang , Masaatzi Higashitani
发明人： Salvatore F. Cagnina , Hao Fang , John Jianshi Wang , Kent Kuohua Chang , Masaatzi Higashitani
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/11546
摘要： A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.
摘要翻译：在第一实施例中用于制造NAND型闪速存储器件的半导体工艺包括可以在制造NOR型闪存产品的生产线上执行的步骤。根据第二实施例的NAND闪存制造工艺简化了处理并且使用较少的掩模，从而降低成本和错误以产生更高的产量。

9. 发明授权

US6057193A Elimination of poly cap for easy poly1 contact for NAND product 失效
标题翻译：消除聚碳酸酯容易使多晶硅接触NAND产品
公开(公告)号：US6057193A
公开(公告)日：2000-05-02
申请号：US61515
申请日：1998-04-16
申请人： John Jianshi Wang , Hao Fang , Masaaki Higashitani
发明人： John Jianshi Wang , Hao Fang , Masaaki Higashitani
IPC分类号： H01L21/28 , H01L21/768 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/768 , H01L27/115 , H01L27/11524
摘要： A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107). A second insulating layer (140) is formed over both the select gate transistor region (105) and the memory cell region (111) and first and second contact openings are formed in the second insulating layer (140) down to the gate structure (107) and the control gate region, wherein a depth (X) through the second insulating layer (140) down to the gate structure (107) and down to the control gate region are approximately the same, thereby eliminating a substantial overetch of the gate structure contact opening.
摘要翻译：形成NAND型快闪存储器件的方法（200）包括以下步骤：在衬底（102）上形成氧化物层（202），并在氧化物层上形成第一导电层（106）。蚀刻第一导电层（106）以在存储单元区域（111）中的选择栅极晶体管区域（105）和浮动栅极结构（106a，106b）中形成栅极结构（107）。然后在存储单元区域（111）之上形成第一绝缘层（110），并且在第一绝缘层（110）之上形成第二导电层（112,118）。在存储单元区域（111）中构图字线（122）以形成控制栅极区域，并且在邻近字线（122）的区域中的衬底（102）中形成源极和漏极区域（130,132）并且在与栅极结构（107）相邻的区域中。在选择栅极晶体管区域（105）和存储单元区域（111）上形成第二绝缘层（140），并且在第二绝缘层（140）中形成第一和第二接触开口至栅极结构（107））和控制栅极区域，其中通过第二绝缘层（140）到达栅极结构（107）并且向下到控制栅极区域的深度（X）大致相同，从而消除了栅极结构的实质上的过蚀刻接触开口

10. 发明授权

US06784061B1 Process to improve the Vss line formation for high density flash memory and related structure associated therewith 有权
标题翻译：改进用于高密度闪速存储器的Vss线形成及其相关结构的方法
公开(公告)号：US06784061B1
公开(公告)日：2004-08-31
申请号：US10179723
申请日：2002-06-25
申请人： Nian Yang , John Jianshi Wang , Hyeon-Seag Kim
发明人： Nian Yang , John Jianshi Wang , Hyeon-Seag Kim
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66825
摘要： One aspect of the invention relates to a method of a NOR-type flash memory and associated structure which comprises forming a flash memory array on a semiconductor substrate in a core region of the flash memory. The flash memory array comprises a plurality of flash memory cells which each have a source region and a drain region in the semiconductor substrate. A first portion of a first dielectric layer is formed over the flash memory array, and contact holes in the first dielectric layer are formed down to source regions of flash memory cells in the core region. A trench is then formed in the first dielectric layer and extends between the two contact holes. The contact holes and trench are then filled with a conductive material, thereby electrically coupling together the source regions of the two flash memory cells. A second portion of the first dielectric layer is then formed over the first portion of the first dielectric layer and the trench, thereby embedding the source contacts and trench in within the first dielectric layer.
摘要翻译：本发明的一个方面涉及NOR型闪速存储器及其相关结构的方法，其包括在闪速存储器的核心区域中的半导体衬底上形成闪存阵列。闪存阵列包括多个闪存单元，每个闪存单元在半导体衬底中具有源区和漏区。第一电介质层的第一部分形成在闪速存储器阵列上，并且第一介电层中的接触孔形成为芯区域中的闪存单元的源区。然后在第一介电层中形成沟槽并在两个接触孔之间延伸。然后用导电材料填充接触孔和沟槽，从而将两个闪存单元的源极区域电耦合在一起。然后在第一介电层和沟槽的第一部分上形成第一介电层的第二部分，从而将源极触点和沟槽嵌入第一介电层内。

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