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1. 发明申请

US20060154417A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060154417A1
公开(公告)日：2006-07-13
申请号：US11330806
申请日：2006-01-11
申请人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
发明人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
IPC分类号： H01L21/8242
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.
摘要翻译：本发明涉及一种制造半导体存储器件的方法，该半导体存储器件被布置成具有设置在上部和下部电极之间的存储元件的交叉点存储器阵列，用于存储数据。本发明包括下电极线，其形成步骤：将设置在下电极线两侧的每个下电极线和绝缘层平坦化，以使其高度大致均匀，从而构图下电极线;存储元件在下电极线上沉积用于存储元件的存储元件层的层沉积步骤，以及在下电极线形成步骤和存储元件层沉积步骤之间或在存储元件层沉积之后进行热处理退火的退火步骤使得可以消除由下电极线的表面的抛光引起的任何损坏。

2. 发明授权

US08030695B2 Structure and manufacturing method of semiconductor memory device 有权
公开(公告)号：US08030695B2
公开(公告)日：2011-10-04
申请号：US12976113
申请日：2010-12-22
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/02
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

3. 发明授权

US07879626B2 Structure and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US07879626B2
公开(公告)日：2011-02-01
申请号：US11274258
申请日：2005-11-16
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

4. 发明申请

US20110089395A1 STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US20110089395A1
公开(公告)日：2011-04-21
申请号：US12976113
申请日：2010-12-22
申请人： Tetsuya OHNISHI , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya OHNISHI , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

5. 发明申请

US20060102943A1 Structure and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US20060102943A1
公开(公告)日：2006-05-18
申请号：US11274258
申请日：2005-11-16
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L29/94
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

6. 发明授权

US07615459B1 Manufacturing method for variable resistive element 有权
标题翻译：可变电阻元件的制造方法
公开(公告)号：US07615459B1
公开(公告)日：2009-11-10
申请号：US12190398
申请日：2008-08-12
申请人： Yushi Inoue , Tetsuya Ohnishi , Kazuya Ishihara , Takahiro Shibiuya , Yasunari Hosoi , Shinobu Yamazaki , Takashi Nakano
发明人： Yushi Inoue , Tetsuya Ohnishi , Kazuya Ishihara , Takahiro Shibiuya , Yasunari Hosoi , Shinobu Yamazaki , Takashi Nakano
IPC分类号： H01L21/20
CPC分类号： H01L45/04 , H01L45/1226 , H01L45/124 , H01L45/146 , H01L45/1633
摘要： A manufacturing method for a variable resistive element according to which a stable switching operation can be achieved with excellent reproducibility is provided. A conductive thin film is deposited on a semiconductor substrate and patterned to a predetermined form, and after that, a first interlayer insulating film is deposited. An opening is then created in a predetermined location on the first interlayer insulating film in such a manner that the upper surface of the conductive thin film is exposed and the thickness of the conductive thin film formed at the bottom of this opening is reduced through processing, and after that, an oxidation process is carried out on the periphery of the exposed conductive thin film. As a result, a variable resistor film is formed in the peripheral region of the opening, and this variable resistor film divides the conductive thin film into a first electrode and a second electrode.
摘要翻译：提供了一种可变电阻元件的制造方法，其中可以以优异的再现性实现稳定的开关操作。将导电薄膜沉积在半导体衬底上并图案化为预定形式，之后沉积第一层间绝缘膜。然后在第一层间绝缘膜上的预定位置处以导电薄膜的上表面露出并且形成在该开口底部的导电薄膜的厚度通过加工而减小的方式形成开口，之后，在露出的导电性薄膜的周围进行氧化处理。结果，在开口的周边区域中形成可变电阻膜，该可变电阻膜将导电薄膜分成第一电极和第二电极。

7. 发明申请

US20090102598A1 SEMICONDUCTOR MEMORY DEVICE WITH VARIABLE RESISTANCE ELEMENT 审中-公开
标题翻译：具有可变电阻元件的半导体存储器件
公开(公告)号：US20090102598A1
公开(公告)日：2009-04-23
申请号：US11995876
申请日：2006-07-05
申请人： Shinobu Yamazaki , Takuya Otabe
发明人： Shinobu Yamazaki , Takuya Otabe
IPC分类号： H01C7/10
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A semiconductor memory device comprising a variable resistance element having a variable resistor between a first electrode and a second electrode, in which electric resistance is changed by applying a voltage pulse between the electrodes comprises at least one reaction preventing film made of a material having an action of blocking the permeation of a reduction species promoting a reduction reaction of the variable resistor and an oxidation species promoting an oxidation reaction of the variable resistor. This prevents the resistance value of the variable resistance element from fluctuating due to a reduction reaction or an oxidation reaction of the variable resistor caused by hydrogen or oxygen existing in the manufacturing steps, so that a semiconductor memory device having a small variation of the resistance value and having a good controllability can be realized with good repeatability.
摘要翻译：一种半导体存储器件，包括具有在第一电极和第二电极之间的可变电阻器的可变电阻元件，其中通过在电极之间施加电压脉冲来改变电阻，包括至少一个由具有动作的材料制成的防反射膜阻止促进可变电阻的还原反应的还原物质的渗透和促进可变电阻器的氧化反应的氧化物质。这样可以防止可变电阻元件的电阻值由于在制造步骤中存在的氢或氧气引起的可变电阻的还原反应或氧化反应而波动，使得电阻值变化小的半导体存储器件并且可以以良好的重复性实现良好的可控性。

8. 发明授权

US06225185B1 Method for fabricating semiconductor memory having good electrical characteristics and high reliability 失效
标题翻译：具有良好的电气特性和高可靠性的半导体存储器的制造方法
公开(公告)号：US06225185B1
公开(公告)日：2001-05-01
申请号：US09427941
申请日：1999-10-27
申请人： Shinobu Yamazaki , Kazuya Ishihara
发明人： Shinobu Yamazaki , Kazuya Ishihara
IPC分类号： H01L2120
CPC分类号： H01L28/55
摘要： After forming a capacitor of a stack type ferroelectric memory device by sequentially patterning an upper electrode, a ferroelectric film and a lower electrode formed above an interlayer insulator film, the capacitor is covered with an oxidation barrier layer. After forming the oxidation barrier layer, the in-process memory device is heat treated at a high temperature in an oxygen-containing atmosphere. The oxidation barrier layer prevents the lower electrode of the capacitor and a barrier metal film between the capacitor and the interlayer insulator film from oxidation during heat treatment. Thus, the occurrence of peelings and hillocks in the lower electrode and the barrier metal film is avoided so that a semiconductor memory has good electrical characteristics and high reliability.
摘要翻译：在层叠型铁电体存储器件的电容器形成之后，通过顺序构图上层电极，铁电体膜和形成在层间绝缘膜上方的下电极，电容器被氧化阻挡层覆盖。在形成氧化阻挡层之后，在含氧气氛中在高温下热处理过程中的记忆装置。氧化阻挡层防止电容器的下电极和电容器与层间绝缘膜之间的阻挡金属膜在热处理期间氧化。因此，避免了在下电极和阻挡金属膜中产生剥离和小丘，使得半导体存储器具有良好的电特性和高可靠性。

9. 发明授权

US08514607B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08514607B2
公开(公告)日：2013-08-20
申请号：US13212457
申请日：2011-08-18
申请人： Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
发明人： Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2213/79
摘要： Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.
摘要翻译：提供一种半导体存储器件，其能够在随机存取编程动作中以期望的可控制性稳定地编程到期望的电阻状态，并且具有可变电阻元件。无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲电阻值被应用。此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。

10. 发明授权

US08482956B2 Semiconductor memory device and method of driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08482956B2
公开(公告)日：2013-07-09
申请号：US13179839
申请日：2011-07-11
申请人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
发明人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
摘要翻译：半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路，电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子，并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

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