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1. 发明申请

US20090102598A1 SEMICONDUCTOR MEMORY DEVICE WITH VARIABLE RESISTANCE ELEMENT 审中-公开
标题翻译：具有可变电阻元件的半导体存储器件
公开(公告)号：US20090102598A1
公开(公告)日：2009-04-23
申请号：US11995876
申请日：2006-07-05
申请人： Shinobu Yamazaki , Takuya Otabe
发明人： Shinobu Yamazaki , Takuya Otabe
IPC分类号： H01C7/10
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A semiconductor memory device comprising a variable resistance element having a variable resistor between a first electrode and a second electrode, in which electric resistance is changed by applying a voltage pulse between the electrodes comprises at least one reaction preventing film made of a material having an action of blocking the permeation of a reduction species promoting a reduction reaction of the variable resistor and an oxidation species promoting an oxidation reaction of the variable resistor. This prevents the resistance value of the variable resistance element from fluctuating due to a reduction reaction or an oxidation reaction of the variable resistor caused by hydrogen or oxygen existing in the manufacturing steps, so that a semiconductor memory device having a small variation of the resistance value and having a good controllability can be realized with good repeatability.
摘要翻译：一种半导体存储器件，包括具有在第一电极和第二电极之间的可变电阻器的可变电阻元件，其中通过在电极之间施加电压脉冲来改变电阻，包括至少一个由具有动作的材料制成的防反射膜阻止促进可变电阻的还原反应的还原物质的渗透和促进可变电阻器的氧化反应的氧化物质。这样可以防止可变电阻元件的电阻值由于在制造步骤中存在的氢或氧气引起的可变电阻的还原反应或氧化反应而波动，使得电阻值变化小的半导体存储器件并且可以以良好的重复性实现良好的可控性。

2. 发明授权

US07276175B2 Semiconductor device fabrication method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07276175B2
公开(公告)日：2007-10-02
申请号：US11062632
申请日：2005-02-23
申请人： Takuya Otabe
发明人： Takuya Otabe
IPC分类号： B44C1/22
CPC分类号： H01L45/1675 , H01L21/31111 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.
摘要翻译：半导体器件制造方法包括：（1）在含Mn的钙钛矿型氧化物的氧化物层上形成图案化掩模层; （2）对氧化物层进行热处理; 和（3）在氧化物层的热处理之后，用含有盐酸，硫酸和硝酸中的至少一种的蚀刻溶液来图案化氧化物层。

3. 发明申请

US20050186334A1 Semiconductor device fabrication method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20050186334A1
公开(公告)日：2005-08-25
申请号：US11062632
申请日：2005-02-23
申请人： Takuya Otabe
发明人： Takuya Otabe
IPC分类号： H01L43/12 , B05D5/12 , H01L21/311 , H01L43/08 , H01L43/10 , H01L45/00
CPC分类号： H01L45/1675 , H01L21/31111 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.
摘要翻译：半导体器件制造方法包括：（1）在含Mn的钙钛矿型氧化物的氧化物层上形成图案化掩模层; （2）对氧化物层进行热处理; 和（3）在氧化物层的热处理之后，用含有盐酸，硫酸和硝酸中的至少一种的蚀刻溶液来图案化氧化物层。

4. 发明授权

US06855973B2 Semiconductor memory device including a capacitor an upper electrode of which being resistant of exfoliation 失效
标题翻译：半导体存储器件包括电容器，其上电极具有剥离性
公开(公告)号：US06855973B2
公开(公告)日：2005-02-15
申请号：US10246773
申请日：2002-09-19
申请人： Takuya Otabe , Masaya Nagata
发明人： Takuya Otabe , Masaya Nagata
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/76 , H01L27/108
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/75
摘要： On a silicon substrate 201, there are formed a silicon oxide 202, an adhesion layer 203 consisting of TiO2, a lower electrode 204 consisting of Pt, a ferroelectric thin film 205, and an upper electrode 206 consisting of Pt. A portion of the ferroelectric thin film adjacent to the upper electrode 206 is formed from a compound with a composition formula of SrBi2 (TaxNb1-x)2O9 where x=0.7. A compound with a value x in the composition formula being greater than 0.7 is used for the portion of the ferroelectric thin film adjacent to the upper electrode 206, so as to generate an appropriate number of grain boundaries on the surface of the ferroelectric film 205, the grain boundaries enabling implementation of anchoring effect between the ferroelectric film 205 and the upper electrode 206, thereby achieving prevention of exfoliation of the upper electrode 206 from the ferroelectric film 205. Therefore, the semiconductor memory device is free from exfoliation of the upper electrode film from the dielectric film and has a good yield.
摘要翻译：在硅衬底201上形成氧化硅202，由TiO 2构成的粘合层203，由Pt组成的下电极204，铁电薄膜205和由Pt组成的上电极206。与上电极206相邻的铁电薄膜的一部分由组成式为SrBi2（TaxNb1-x）2O9的化合物形成，其中x = 0.7。对于与上电极206相邻的铁电薄膜的部分，使用组成式中的值x大于0.7的化合物，以在铁电薄膜205的表面上产生适当数量的晶界，能够实现强电介质膜205与上部电极206之间的固定效果的晶界，从而可以防止上部电极206从铁电体膜205剥离。因此，半导体存储元件没有上部电极膜的剥离从电介质膜得到良好的收率。

5. 发明授权

US07743488B2 Manufacturing method for variable resistive element 失效
标题翻译：可变电阻元件的制造方法
公开(公告)号：US07743488B2
公开(公告)日：2010-06-29
申请号：US11447293
申请日：2006-06-06
申请人： Yukio Tamai , Takuya Otabe
发明人： Yukio Tamai , Takuya Otabe
IPC分类号： H01C10/00 , H01C17/00 , H01C17/28
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1641 , H01L45/1675 , Y10T29/49082 , Y10T29/49101 , Y10T29/49124 , Y10T29/49204
摘要： In the case where a variable resistive element, which is made of a variable resistor provided between a first and second electrodes, and of which the electrical resistance varies by applying a voltage pulse between the two electrodes, is applied to a resistance nonvolatile memory, there is a range of the resistance value of the variable resistive element in a low resistance state where the nonvolatile memory can operate normally. In the conventional manufacturing method the resistance value of the variable resistive element is too low, therefore, it can not be controlled within a desired range of the resistance value. A step of carrying out of a reduction process is provided at any point after the step of forming a variable resistor material as a film, it has thereby become possible to increase the resistance value of the variable resistive element, which is too low in the conventional method.
摘要翻译：在由可变电阻器构成的可变电阻元件（其设置在第一和第二电极之间并且其电阻通过在两个电极之间施加电压脉冲而变化）施加到电阻非易失性存储器的情况下，在那里是在非易失性存储器能够正常工作的低电阻状态下的可变电阻元件的电阻值的范围。在传统的制造方法中，可变电阻元件的电阻值太低，因此不能将其控制在电阻值的期望范围内。在形成可变电阻器材料作为膜的步骤之后的任何点都提供了进行还原处理的步骤，因此可以增加可变电阻元件的电阻值，其在常规方法中太低方法。

6. 发明申请

US20080135973A1 SEMICONDUCTOR DEVICE COMPRISING HIGH-WITHSTAND VOLTAGE MOSFET AND ITS MANUFACTURING METHOD 有权
标题翻译：包含高耐压MOSFET的半导体器件及其制造方法
公开(公告)号：US20080135973A1
公开(公告)日：2008-06-12
申请号：US11947214
申请日：2007-11-29
申请人： Satoshi HIKIDA , Takuya Otabe , Hisashi Yonemoto
发明人： Satoshi HIKIDA , Takuya Otabe , Hisashi Yonemoto
IPC分类号： H01L23/58 , H01L21/04
CPC分类号： H01L29/7834 , H01L29/1083 , H01L29/4236 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.
摘要翻译：高耐压MOSFET包括形成在半导体衬底上的高耐压有源区的沟槽部分，通过注入导电性杂质形成在沟槽部分两侧的高耐压电压有源区上的两个多晶硅层类型与高耐压有源区相反，通过在高耐压的表面中注入与高耐压电压有源区相反的导电类型的杂质形成在沟槽部两侧的两个杂质扩散漂移层在多晶硅层下方的有源区以及在沟槽部分的底部和侧表面上形成的栅极电极以及靠近沟槽部分的多晶硅层的相邻区域的端面和上表面以及源极和漏极区域形成在除了被栅电极覆盖的相邻区域之外的两个多晶硅层中。

7. 发明授权

US07851853B2 Semiconductor device comprising high-withstand voltage MOSFET and its manufacturing method 有权
标题翻译：包括高耐压MOSFET的半导体器件及其制造方法
公开(公告)号：US07851853B2
公开(公告)日：2010-12-14
申请号：US11947214
申请日：2007-11-29
申请人： Satoshi Hikida , Takuya Otabe , Hisashi Yonemoto
发明人： Satoshi Hikida , Takuya Otabe , Hisashi Yonemoto
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L29/7834 , H01L29/1083 , H01L29/4236 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.
摘要翻译：高耐压MOSFET包括形成在半导体衬底上的高耐压有源区的沟槽部分，通过注入导电性杂质形成在沟槽部分两侧的高耐压电压有源区上的两个多晶硅层类型与高耐压有源区相反，通过在高耐压的表面中注入与高耐压电压有源区相反的导电类型的杂质形成在沟槽部两侧的两个杂质扩散漂移层在多晶硅层下方的有源区以及在沟槽部分的底部和侧表面上形成的栅极电极以及靠近沟槽部分的多晶硅层的相邻区域的端表面和上表面以及源极和漏极区域形成在除了被栅电极覆盖的相邻区域之外的两个多晶硅层中。

8. 发明申请

US20060281277A1 Manufacturing method for variable resistive element 失效
标题翻译：可变电阻元件的制造方法
公开(公告)号：US20060281277A1
公开(公告)日：2006-12-14
申请号：US11447293
申请日：2006-06-06
申请人： Yukio Tamai , Takuya Otabe
发明人： Yukio Tamai , Takuya Otabe
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1641 , H01L45/1675 , Y10T29/49082 , Y10T29/49101 , Y10T29/49124 , Y10T29/49204
摘要： In the case where a variable resistive element, which is made of a variable resistor provided between a first and second electrodes, and of which the electrical resistance varies by applying a voltage pulse between the two electrodes, is applied to a resistance nonvolatile memory, there is a range of the resistance value of the variable resistive element in a low resistance state where the nonvolatile memory can operate normally. In the conventional manufacturing method the resistance value of the variable resistive element is too low, therefore, it can not be controlled within a desired range of the resistance value. A step of carrying out of a reduction process is provided at any point after the step of forming a variable resistor material as a film, it has thereby become possible to increase the resistance value of the variable resistive element, which is too low in the conventional method.
摘要翻译：在由可变电阻器构成的可变电阻元件（其设置在第一和第二电极之间并且其电阻通过在两个电极之间施加电压脉冲而变化）施加到电阻非易失性存储器的情况下，在那里是在非易失性存储器能够正常工作的低电阻状态下的可变电阻元件的电阻值的范围。在传统的制造方法中，可变电阻元件的电阻值太低，因此不能将其控制在电阻值的期望范围内。在形成可变电阻器材料作为膜的步骤之后的任何点都提供了进行还原处理的步骤，因此可以增加可变电阻元件的电阻值，其在常规方法中太低方法。

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