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1. 发明授权

US06298355B1 Computer system 失效
标题翻译：电脑系统
公开(公告)号：US06298355B1
公开(公告)日：2001-10-02
申请号：US09269023
申请日：1999-03-18
申请人： Teruo Tanaka , Tadayuki Sakakibara , Hiromitsu Maeda
发明人： Teruo Tanaka , Tadayuki Sakakibara , Hiromitsu Maeda
IPC分类号： G06F1700
CPC分类号： G06F13/1668
摘要： A storage control unit of a computer system in which main storage is shared between one through a plurality of processors, is provided with transfer control means for holding therein address information in a first area of the main storage, in which desired data specified by an arbitrary processor is stored, address information in a second area of the main storage device, to which the desired data is to be transferred, and information about the length of the desired data, and transfer means for reading the data stored in the first area and storing the data in the second area under the control of the transfer control means. Owing to these configurations, the storage control unit is capable of executing a copy of data from the first area to the second area separately from the processors according to instructions from each processor. Thus, the load on each processor can be reduced. Since a processor bus may be unused in data copying when the plurality of processors are connected to the processor bus, the load on the processor bus can be greatly reduced.
摘要翻译：在一个至多个处理器之间共享主存储器的计算机系统的存储控制单元设置有传送控制装置，用于在主存储器的第一区域中保存地址信息，其中由任意的处理器被存储在主存储装置的第二区域中，要传送期望数据的地址信息以及关于期望数据长度的信息，以及用于读取存储在第一区域中的数据并存储在传输控制装置的控制下的第二区域中的数据。由于这些配置，存储控制单元能够根据来自每个处理器的指令从处理器执行从第一区域到第二区域的数据副本。因此，可以减少每个处理器上的负载。由于当多个处理器连接到处理器总线时，在数据复制中可能未使用处理器总线，因此可以大大减少处理器总线上的负载。

2. 发明授权

US5530881A Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs 失效
标题翻译：用于处理与混合型程序和单独类型程序相对应的不同指令集架构的矢量处理装置
公开(公告)号：US5530881A
公开(公告)日：1996-06-25
申请号：US894633
申请日：1992-06-05
申请人： Yasuhiro Inagami , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Tadayuki Sakakibara
发明人： Yasuhiro Inagami , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Tadayuki Sakakibara
IPC分类号： G06F9/318 , G06F9/38 , G06F15/78 , G06F9/30
CPC分类号： G06F9/30189 , G06F15/8076 , G06F9/30036 , G06F9/3877
摘要： A vector processor system for processing vector instructions and scaler instructions fetched from storages includes a memory storage, a first and a second scaler processing units connected to the memory storage, a vector processing unit being connected to the memory storage and the two scaler processing units and for processing a vector instruction fetched from the memory storage during processing of scaler instruction/vector instruction separate type programs and a vector instruction received from the second scaler processing unit during processing of scaler instruction/vector instruction mingled type programs. More particularly, for scaler instruction/vector instruction mingled type programs, the vector processing unit receives the vector instruction from the scaler processing unit, whereas for scaler instruction/vector instruction separate type programs, the vector processing unit retrieves the vector instruction directly from the memory storage.
摘要翻译：用于处理从存储器取出的向量指令和缩放器指令的向量处理器系统包括存储器存储器，连接到存储器存储器的第一和第二定标器处理单元，连接到存储器存储器和两个定标器处理单元的矢量处理单元，以及用于在缩放器指令/向量指令混合类型程序的处理期间处理在缩放器指令/向量指令单独类型程序和从第二缩放器处理单元接收的向量指令的处理期间处理从存储器存储器获取的向量指令。更具体地说，对于缩放器指令/向量指令混合型程序，向量处理单元从缩放器处理单元接收向量指令，而对于缩放器指令/向量指令单独类型程序，向量处理单元直接从存储器检索向量指令存储。

3. 发明授权

US5506980A Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory 失效
标题翻译：利用共享辅助存储器并行处理大数据阵列的方法和装置
公开(公告)号：US5506980A
公开(公告)日：1996-04-09
申请号：US964845
申请日：1992-10-22
申请人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai , Teruo Tanaka , Tadayuki Sakakibara
发明人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai , Teruo Tanaka , Tadayuki Sakakibara
IPC分类号： G06F15/173 , G06F12/00 , G06F13/00
CPC分类号： G06F15/17368
摘要： In a multiprocessor system having a plurality of main memories and a shared extended memory, each main memory is associated with an extended memory partial write control. When an extended memory partial write instruction is issued, tag information identifying updated portions of main memory data is transferred to the associated extended memory partial write control along with the main memory data. Each time a subblock of the main memory data arrives, the extended memory partial write control performs a partial write operation to substitute those portions of the main memory data which are identified by the tag information for the corresponding portions of a data subblock in a specified extended memory area. During this partial write operation, that specified extended memory area is kept locked.
摘要翻译：在具有多个主存储器和共享扩展存储器的多处理器系统中，每个主存储器与扩展存储器部分写入控制相关联。当发出扩展存储器部分写入指令时，识别主存储器数据的更新部分的标签信息与主存储器数据一起传送到相关联的扩展存储器部分写入控制。每当主存储器数据的子块到达时，扩展存储器部分写入控制执行部分写入操作，以将由标签信息识别的主存储器数据的那些部分替换为指定扩展中的数据子块的对应部分记忆区。在该部分写入操作期间，指定的扩展内存区域被保持锁定。

4. 发明授权

US5392443A Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data 失效
标题翻译：矢量处理器具有分配了倾斜地址的存储器，适用于并发取出属于相同向量数据的多个向量元素
公开(公告)号：US5392443A
公开(公告)日：1995-02-21
申请号：US855056
申请日：1992-03-19
申请人： Tadayuki Sakakibara , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Teruo Tanaka , Tadaaki Isobe , Shigeko Yazawa , Masanao Ito
发明人： Tadayuki Sakakibara , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Teruo Tanaka , Tadaaki Isobe , Shigeko Yazawa , Masanao Ito
IPC分类号： G06F12/06 , G06F15/78 , G06F15/16
CPC分类号： G06F15/8076 , G06F12/0607
摘要： A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.
摘要翻译：在存储控制单元部分中采用多个存储控制单元; 此外，与这些存储控制单元相关联地采用两个请求者模块。每个存储器模块由与存储控制单元一样多的存取组组构成。访问存储组以并行方式操作，并且可以从任何一个存储控制单元访问。在元素分配中，每个请求者模块中的多个请求控制单元和每个向量寄存器单元中的多个向量数据控制器分别被分配从零开始的序列号。对于矢量数据控制器，分配给它的数字被请求模块计数除以获得余数，使得矢量数据控制器被分配给具有与其余值相同数目的请求模块。此外，请求队列设置在每个优先级单元之前的阶段，并且请求发送单元被布置为在其中存储请求队列的状态并且控制来自每个请求控制单元的请求传输。根据分别适合的偏移方案将地址分配给相应的存储器模块，存储体组和存储体。

5. 发明授权

US5617575A Interprocessor priority control system for multivector processor 失效
标题翻译：多处理器处理器优先级控制系统
公开(公告)号：US5617575A
公开(公告)日：1997-04-01
申请号：US170743
申请日：1993-12-21
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F12/00 , G06F15/16
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

6. 发明授权

US5590353A Vector processor adopting a memory skewing scheme for preventing degradation of access performance 失效
标题翻译：矢量处理器采用存储器偏移方案来防止访问性能下降
公开(公告)号：US5590353A
公开(公告)日：1996-12-31
申请号：US275388
申请日：1994-07-15
申请人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami
发明人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami
IPC分类号： G06F9/345 , G06F9/38 , G06F12/00 , G06F12/06 , G06F15/78 , G06F17/16 , G06F15/16
CPC分类号： G06F15/8061 , G06F9/345 , G06F9/3455 , G06F9/3824
摘要： A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.
摘要翻译：矢量处理器包括存储控制装置，该存储控制装置包括具有地址解码单元的访问请求缓冲单元，地址解码单元具有与属于同一机器系列的所有向量处理器模型对应的地址解码器电路。通过使用模型ID信号，地址解码由选择器选择性地启用。地址解码单元对属于同一机器系列的处理器的所有元素并行因子对存储器模块的地址分配进行偏移或偏移的周期性进行均衡。提供访问请求队列优先于包含在存储控制装置中的访问请求优先级确定单元的必要数量级。

7. 发明授权

US5339429A Parallel processing system and compiling method used therefor 失效
标题翻译：并行处理系统及其编译方法
公开(公告)号：US5339429A
公开(公告)日：1994-08-16
申请号：US880544
申请日：1992-05-08
申请人： Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki , Tadayuki Sakakibara , Katsuyoshi Kitai
发明人： Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki , Tadayuki Sakakibara , Katsuyoshi Kitai
IPC分类号： G06F9/45 , G06F12/02 , G06F15/167 , G06F9/44 , G06F12/12
CPC分类号： G06F8/44 , G06F12/0284 , G06F15/167
摘要： A parallel processing system includes tightly coupled multiprocessors. Each multiprocessor incorporates a local extended storage device which is a secondary storage device for a main storage device. The tightly coupled multiprocessors are connected with each other through a shared extended storage device. A compiler or preprocessor for the system analyzes the data to be allocated on the extended storage devices so that large scaled data accessed from each tightly-coupled multiprocessor are allocated on the local extended storage whereas the data to be accessed from a plurality of tightly-coupled multiprocessors are allocated on the shared extended storage.
摘要翻译：并行处理系统包括紧密耦合的多处理器。每个多处理器都包含一个本地扩展存储设备，它是主存储设备的辅助存储设备。紧密耦合的多处理器通过共享扩展存储设备彼此连接。用于系统的编译器或预处理器分析在扩展存储设备上要分配的数据，使得从每个紧密耦合的多处理器访问的大规模数据被分配在本地扩展存储器上，而从多个紧耦合多处理器分配在共享扩展存储上。

8. 发明授权

US5857110A Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors 失效
标题翻译：优先级控制，并行切换向量处理器的优先级，用于矢量处理器共享的存储器模块的多个优先级电路
公开(公告)号：US5857110A
公开(公告)日：1999-01-05
申请号：US760525
申请日：1996-12-05
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

9. 发明授权

US5809539A Processor system having address allocation and address lock capability adapted for a memory comprised of synchronous DRAMs 失效
标题翻译：具有地址分配和地址锁定能力的处理器系统适用于由同步DRAM组成的存储器
公开(公告)号：US5809539A
公开(公告)日：1998-09-15
申请号：US637283
申请日：1996-04-24
申请人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki
IPC分类号： G06F12/06 , G06F13/16 , G06F12/00
CPC分类号： G06F13/1631 , G06F12/0607
摘要： In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.
摘要翻译：为了利用包括同步DRAM等的多个存储器组的行地址锁定操作模式并且被划分为多个真实存储体组，例如，比存储器组多于多个每个跨越真实银行集团的逻辑组。以块交织的方式，以每个逻辑组为单位分配地址。当由给定请求者发出的一系列请求包括访问同一存储体中相同行地址的多个请求时，该请求者请求该行地址被锁定以供多个请求访问。锁请求由行地址管理单元保留。当来自另一请求者的后续请求请求访问除同一存储体中的锁定地址之外的行地址时，优先级电路优先选择已经锁定存储器的初始请求者的预定数量的请求，优先于另一请求请求者

10. 发明授权

US5867679A Parallel processor system with asynchronous data transmission by a data producing processor to a data using processor employing controlled execution of a program by the data using processor for processing the data 失效
标题翻译：并行处理器系统，其通过数据产生处理器将异步数据传输到使用处理器的数据的数据采用由数据使用处理器处理数据的数据的受控执行程序
公开(公告)号：US5867679A
公开(公告)日：1999-02-02
申请号：US647773
申请日：1991-01-30
申请人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
发明人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F9/44 , G06F15/17 , G06F15/80 , G06F15/82
CPC分类号： G06F15/8015 , G06F9/4494 , G06F15/17
摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
摘要翻译：并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。

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