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    • 1. 发明授权
      US5572157A Digital phase-looked loop circuit 失效
    • Digital phase-looked loop circuit
    • 数字相位环路电路
    • US5572157A
    • 1996-11-05
    • US21854
    • 1993-02-24
    • Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
    • Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
    • H03K5/00 , H03L7/06 , H03L7/08 , H03L7/093 , H03L7/10 , H03L7/085
    • H03L7/10 , H03L7/093
    • Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator 8 for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
    • 来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。 在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。 由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF5。 LPF5还包括相位补偿器6和周期补偿器8，用于通过数字滤波器7中的内相位误差DELTA N补偿控制延迟体验。使用由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1 用于确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并作为误差数据Ne存储。 因此，采集时间缩短，稳态误差的数量也减少。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US5841303A Digital phase-locked loop circuit 失效
    • Digital phase-locked loop circuit
    • 数字锁相环电路
    • US5841303A
    • 1998-11-24
    • US742678
    • 1996-10-31
    • Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
    • Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
    • H03K5/00 , H03L7/06 , H03L7/08 , H03L7/093 , H03L7/10 , H03L7/085
    • H03L7/10 , H03L7/093
    • Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
    • 来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。 在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。 由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF 5。 LPF5还包括相位补偿器6和周期补偿器，用于通过数字滤波器7中的内部相位误差DELTA N来补偿控制延迟体验。由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1用于 确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并存储在其中作为误差数据Ne。 因此，采集时间缩短，稳态误差的数量也减少。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5625632A Magnetic disk drive including a data discrimination apparatus capable of correcting signal waveform distortion due to intersymbol interference 失效
    • Magnetic disk drive including a data discrimination apparatus capable of correcting signal waveform distortion due to intersymbol interference
    • 磁盘驱动器包括能够校正由于符号间干扰引起的信号波形失真的数据鉴别装置
    • US5625632A
    • 1997-04-29
    • US319725
    • 1994-10-07
    • Yoshiteru Ishida , Kazunori Iwabuchi , Hideyuki Yamakawa , Hiromi Matsushige
    • Yoshiteru Ishida , Kazunori Iwabuchi , Hideyuki Yamakawa , Hiromi Matsushige
    • G11B20/10 , G06F11/10 , H03M13/00
    • G11B20/10009
    • A data discrimination apparatus which is capable of correcting a decrease in amplitude of a signal to be data discriminated by a correction value so as to correct the bit itself which was used as a target bit to determine the correction value. A decision circuit preliminarily classifies an equalizer output into symbols "0" and "1" to obtain a run length of the symbol "0" with respect to a given symbol "1" (the target bit). A correction value generating circuit includes a memory device which contains correction values in correspondence with all the possible values of the run length, and outputs one of the correction values out of the memory device in response to an output from the decision circuit. A delay circuit delays the equalizer output by a time which is required until the correction value is output. An operation circuit adds the selected correction value to the delayed equalizer output, to correct the same. The thus corrected equalizer output is data discriminated in a data discrimination circuit, with a lowered error rate owing to the correction.
    • 一种数据识别装置，其能够校正由校正值识别的要被数据的信号的幅度的降低，以便校正用作目标位的位本身以确定校正值。 判定电路预先将均衡器输出分类为符号“0”和“1”，以获得相对于给定符号“1”（目标位）的符号“0”的游程长度。 校正值产生电路包括存储器件，其存储与游程长度的所有可能值相对应的校正值，并且响应于来自判定电路的输出将一个校正值输出存储器件。 延迟电路使均衡器输出延迟所需的时间，直到校正值被输出。 操作电路将所选择的校正值与延迟均衡器输出相加，以校正相同的值。 这样校正的均衡器输出是在数据鉴别电路中鉴别的数据，由于校正而导致的误差率降低。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5553104A Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal 失效
    • Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal
    • 具有用于从输入数据信号中提取时钟信号的时钟定时提取电路的信息记录/再现装置
    • US5553104A
    • 1996-09-03
    • US266779
    • 1994-06-29
    • Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
    • Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
    • G11B20/14 , G11B27/30 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/183 , H04L7/033 , H03D3/24
    • H03L7/0996 , G11B20/1403 , G11B27/30 , H03L7/081 , H03L7/183 , H04L7/0337
    • A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.
    • 用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器，用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路，用于调整频率以使误差信号接近 根据相位误差信号输出零，并输出具有相互不同的相位差的多个时钟信号，用于基于选择信号输出多个时钟信号中的一个的选择电路，用于确定其中之一的相位差判定电路 具有最小相位误差（Vdet）的多个时钟信号，并且产生用于选择具有最小相位差的时钟信号的选择信号，以及用于阻止相位比较器的输出的冻结电路，直到具有最小相位误差的时钟信号 被选中。 信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路，上述时钟定时提取电路和解码器电路。 时钟定时提取电路从AGC电路的输出信号中提取时钟信号，解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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