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1. 发明授权

US5822605A Parallel processor system with a broadcast message serializing circuit provided within a network 失效
标题翻译：具有在网络内提供的广播消息序列化电路的并行处理器系统
公开(公告)号：US5822605A
公开(公告)日：1998-10-13
申请号：US408561
申请日：1995-03-22
申请人： Tatsuo Higuchi , Tadaaki Isobe , Junji Nakagoshi , Shigeo Takeuchi , Tatsuru Toba , Yoshiko Yasuda , Teruo Tanaka , Takayuki Nakagawa , Yuji Saeki
发明人： Tatsuo Higuchi , Tadaaki Isobe , Junji Nakagoshi , Shigeo Takeuchi , Tatsuru Toba , Yoshiko Yasuda , Teruo Tanaka , Takayuki Nakagawa , Yuji Saeki
IPC分类号： G06F15/173 , H04L12/56 , G06F13/00 , H04L12/50
CPC分类号： H04L45/06 , G06F15/17381
摘要： In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks. These schemes all apply where long messages are transmitted through worm-hole routing.
摘要翻译：在包括构成网络的多个处理器元件的并行处理器系统中，希望向多个目的地处理器元件广播数据的源处理器元件向广播交换机发送包含目标数据的广播请求消息。广播交换机将接收的消息转换成广播消息，并通过网络将其发送到目的地。如果与广播交换机并行发送的多个广播请求消息被序列化，从而在网络上一次只能发送一个广播消息。这可以防止不同广播消息之间发生死锁。用于发送广播请求消息的路由和用于发送广播消息的路由被布置为不彼此重叠。这抑制了任何广播请求消息和广播消息之间的死锁。广播交换机被替换为部分网络之一。这些方案都适用于通过蠕虫孔路由传输长消息的情况。

2. 发明授权

US5787301A Parallel computer system 失效
标题翻译：并行计算机系统
公开(公告)号：US5787301A
公开(公告)日：1998-07-28
申请号：US407843
申请日：1995-03-21
申请人： Osamu Arakawa , Tadaaki Isobe , Toshimitsu Ando , Masato Ishii , Shigeo Takeuchi
发明人： Osamu Arakawa , Tadaaki Isobe , Toshimitsu Ando , Masato Ishii , Shigeo Takeuchi
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , G06F15/80
CPC分类号： G06F13/4022
摘要： A parallel computer system includes a plurality of processor units, a data transfer network for interconnecting the processor units, a synchronizing network for allowing program execution to be performed synchronously by the individual processor units, a connecting unit for connecting the individual processor units and the synchronizing network, and an input unit connected to the synchronizing network. The connecting unit connects selectively the individual processor units to the synchronizing network in accordance with information inputted via the input unit. With the parallel computer system, a program can be executed synchronously in parallel by using a desired number of processor units of those incorporated in the system, whereby availability of processor resources of the system can be enhanced.
摘要翻译：并行计算机系统包括多个处理器单元，用于互连处理器单元的数据传输网络，用于允许由各个处理器单元同步执行程序执行的同步网络，用于连接各个处理器单元的连接单元和用于连接各个处理器单元的同步网络和连接到同步网络的输入单元。连接单元根据经由输入单元输入的信息将各个处理器单元选择性地连接到同步网络。利用并行计算机系统，可以通过使用系统中并入的所需数量的处理器单元并行地执行程序，由此可以提高系统的处理器资源的可用性。

3. 发明授权

US5857110A Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors 失效
标题翻译：优先级控制，并行切换向量处理器的优先级，用于矢量处理器共享的存储器模块的多个优先级电路
公开(公告)号：US5857110A
公开(公告)日：1999-01-05
申请号：US760525
申请日：1996-12-05
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

4. 发明授权

US5392443A Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data 失效
标题翻译：矢量处理器具有分配了倾斜地址的存储器，适用于并发取出属于相同向量数据的多个向量元素
公开(公告)号：US5392443A
公开(公告)日：1995-02-21
申请号：US855056
申请日：1992-03-19
申请人： Tadayuki Sakakibara , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Teruo Tanaka , Tadaaki Isobe , Shigeko Yazawa , Masanao Ito
发明人： Tadayuki Sakakibara , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Teruo Tanaka , Tadaaki Isobe , Shigeko Yazawa , Masanao Ito
IPC分类号： G06F12/06 , G06F15/78 , G06F15/16
CPC分类号： G06F15/8076 , G06F12/0607
摘要： A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.
摘要翻译：在存储控制单元部分中采用多个存储控制单元; 此外，与这些存储控制单元相关联地采用两个请求者模块。每个存储器模块由与存储控制单元一样多的存取组组构成。访问存储组以并行方式操作，并且可以从任何一个存储控制单元访问。在元素分配中，每个请求者模块中的多个请求控制单元和每个向量寄存器单元中的多个向量数据控制器分别被分配从零开始的序列号。对于矢量数据控制器，分配给它的数字被请求模块计数除以获得余数，使得矢量数据控制器被分配给具有与其余值相同数目的请求模块。此外，请求队列设置在每个优先级单元之前的阶段，并且请求发送单元被布置为在其中存储请求队列的状态并且控制来自每个请求控制单元的请求传输。根据分别适合的偏移方案将地址分配给相应的存储器模块，存储体组和存储体。

5. 发明授权

US5617575A Interprocessor priority control system for multivector processor 失效
标题翻译：多处理器处理器优先级控制系统
公开(公告)号：US5617575A
公开(公告)日：1997-04-01
申请号：US170743
申请日：1993-12-21
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F12/00 , G06F15/16
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

6. 发明授权

US6119150A Message passing distributed shared memory system that eliminates unnecessary software controlled cache flushes or purges 失效
标题翻译：消息传递分布式共享内存系统，消除了不必要的软件控制的缓存刷新或清除
公开(公告)号：US6119150A
公开(公告)日：2000-09-12
申请号：US789184
申请日：1997-01-24
申请人： Hiroaki Fujii , Tadaaki Isobe , Makoto Koga , Hideya Akashi
发明人： Hiroaki Fujii , Tadaaki Isobe , Makoto Koga , Hideya Akashi
IPC分类号： G06F15/17 , G06F12/08 , G06F15/167 , G06F13/00
CPC分类号： G06F12/0837 , G06F12/0813
摘要： An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.
摘要翻译：采用根据来自存储控制器的请求执行高速缓存一致性控制的指令处理器。存储控制器设置有高速缓存一致性控制处理电路，其对作为通过数据传送发生的主存储器访问的目的地的地址执行高速缓存一致性控制。同时，高速缓存一致性控制处理电路在数据传送过程中对每条高速缓存线执行一次高速缓存一致性控制处理。消除了与数据传输有关的软件执行的高速缓存一致性控制处理，提高了包括缓存存储器控制在内的数据传输效率，并减少了对程序的限制。

7. 发明授权

US5367654A Method and apparatus for controlling storage in computer system utilizing forecasted access requests and priority decision circuitry 失效
标题翻译：利用预测的访问请求和优先级决定电路来控制计算机系统中的存储的方法和装置
公开(公告)号：US5367654A
公开(公告)日：1994-11-22
申请号：US337070
申请日：1989-04-12
申请人： Masao Furukawa , Tadaaki Isobe , Shigeko Yazawa
发明人： Masao Furukawa , Tadaaki Isobe , Shigeko Yazawa
IPC分类号： G06F9/46 , G06F13/14 , G06F12/00
CPC分类号： G06F9/52
摘要： A storage control apparatus of a computer system having a plurality of transfer pipelines issuing access requests to a plurality of memory banks of a storage device. Each memory bank is independently accessible in response to an access instruction from a vector processing device. Each of the transfer pipelines includes a plurality of access request control devices to which the access instruction from the vector processing device is allocated in association with elements of a vector. The access request control devices simultaneously issue in response to an access instruction a plurality of access requests. Each transfer pipeline also includes a priority decision device which detects whether or not the access requests forecasted to be issued from the plural access request control devices contend with the access requests issued from the plural access request control devices of another transfer pipeline. In a case where it is detected that a contention takes place, processing of the access requests of another transfer pipeline effecting the succeeding access instruction is set to a wait state such that the access requests of the pertinent transfer pipeline effecting the preceding access instruction are preferentially processed.
摘要翻译：一种计算机系统的存储控制装置，具有向存储装置的多个存储体发出访问请求的多个传送管线。响应于来自向量处理设备的访问指令，每个存储体可独立访问。每个传输管线包括多个访问请求控制设备，来自向量处理设备的访问指令与向量的元素相关联地分配给该访问请求控制设备。访问请求控制装置响应于访问指令同时发出多个访问请求。每个传送管线还包括优先级决定装置，其检测从多个访问请求控制装置预测要发出的访问请求是否与从另一传送流水线的多个访问请求控制装置发出的访问请求相抵触。在检测到发生竞争的情况下，将影响后续访问指令的另一传送管线的访问请求的处理设置为等待状态，使得执行前一访问指令的相关传输管线的访问请求优先处理。

8. 发明授权

US06336190B1 Storage apparatus 失效
标题翻译：储存装置
公开(公告)号：US06336190B1
公开(公告)日：2002-01-01
申请号：US09268715
申请日：1999-03-17
申请人： Toshihiro Yamagishi , Tadaaki Isobe
发明人： Toshihiro Yamagishi , Tadaaki Isobe
IPC分类号： G06F1338
CPC分类号： G06F3/0601 , G06F13/4243 , G06F2003/0692 , H04L7/0008
摘要： A memory system for use in a high-speed computer system, such as a super computer, has synchronous-type storage elements organized in groups for storing data. A storage control section has a clock generator circuit that generates parallel transfer clock signals that compensate for overall transfer delay when data is transferred to the storage elements. Each of the storage elements groups has a phase-locked locked loop circuit that outputs timing signals for accepting data, including address and control signals, etc., at the storage elements. Data is read out from the storage elements to a return data holding circuit of the storage control section using return parallel transfer clock signals, which are controlled by a control section phase-locked loop circuit that receives as an input a timing output of the phase-locked loop circuit of one of the storage element groups. A clock distribution circuit controls the supply of clock signals to a flip-flop group in the return data holding circuit. A timing signal supplied to one of the flip-flop circuits is returned to the storage control phase-locked loop circuit for controlling the timing of the acceptance of the transferred data in the flip-flop group of the return data holding circuit.
摘要翻译：用于诸如超级计算机的高速计算机系统中的存储器系统具有组合成用于存储数据的同步型存储元件。存储控制部分具有时钟发生器电路，该时钟发生器电路产生并行传输时钟信号，以在数据被传送到存储元件时补偿整个传输延迟。每个存储元件组具有锁存锁定环电路，其在存储元件处输出用于接收包括地址和控制信号等的数据的定时信号。数据从存储元件读出到存储控制部分的返回数据保持电路，使用返回并行传输时钟信号，其由控制部分锁相环电路控制，控制部分锁相环电路作为输入接收相位 - 一个存储元件组的锁定回路电路。时钟分配电路控制向返回数据保持电路中的触发器组提供时钟信号。提供给触发器电路中的一个的定时信号被返回到存储控制锁相环电路，用于控制在返回数据保持电路的触发器组中接收传送数据的定时。

9. 发明授权

US5729550A Data transmitter-receiver 失效
标题翻译：数据发射机 - 接收机
公开(公告)号：US5729550A
公开(公告)日：1998-03-17
申请号：US618787
申请日：1996-03-20
申请人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
发明人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
IPC分类号： G06F5/06 , G06K5/04 , G11B5/00 , G11B20/20
CPC分类号： G06F5/06
摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.
摘要翻译：在信息处理系统中的多个单元之间发送和接收信号时，可以在由周期（频率）相同但不一定相位的异步时钟操作的电路之间发送和接收信号，从而允许信息处理系统在较短的时钟周期内运行。布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。延迟电路由决定结果自动控制。

10. 发明授权

US5822329A Data-transmitter-receiver 失效
标题翻译：数据发射机 - 接收机
公开(公告)号：US5822329A
公开(公告)日：1998-10-13
申请号：US949783
申请日：1997-10-14
申请人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
发明人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
IPC分类号： G06F5/06 , G06K5/04 , G11B5/00
CPC分类号： G06F5/06
摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.
摘要翻译：在信息处理系统中的多个单元之间的发送和接收信号中，可以在由周期（频率）相同但不必相同的异步时钟操作的电路之间发送和接收信号，从而允许信息处理系统在较短的时钟周期内运行。布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。延迟电路由决定结果自动控制。

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