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1. 发明授权

US08176451B2 Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium 有权
标题翻译：行为综合装置，行为综合方法和计算机可读记录介质
公开(公告)号：US08176451B2
公开(公告)日：2012-05-08
申请号：US12569043
申请日：2009-09-29
申请人： Takao Toi , Noritsugu Nakamura , Yoshinosuke Kato , Toru Awashima , Taro Fujii , Toshiro Kitaoka , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Noritsugu Nakamura , Yoshinosuke Kato , Toru Awashima , Taro Fujii , Toshiro Kitaoka , Koichiro Furuta , Masato Motomura
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.
摘要翻译：行为综合装置包括获取单元，调度单元和生成单元。采集单元获取描述半导体集成电路的操作的行为级别描述。调度单元将所获取的行为级别描述分为N级描述，并且进行调度，使得N级描述中的输入/输出操作和计算被流水线化。生成单元基于N级描述和由调度单元执行的调度结果以分别对应于N级描述的级电路和控制可能的2N的状态控制电路来生成寄存器传送级别描述 -1级控制状态的半导体集成电路。生成单元以禁止不需要操作的级电路的操作的方式生成寄存器传送级别描述。

2. 发明授权

US08275973B2 Reconfigurable device 有权
标题翻译：可重新配置的设备
公开(公告)号：US08275973B2
公开(公告)日：2012-09-25
申请号：US12457649
申请日：2009-06-17
申请人： Takao Toi , Toru Awashima , Taro Fujii , Toshiro Kitaoka , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Toru Awashima , Taro Fujii , Toshiro Kitaoka , Koichiro Furuta , Masato Motomura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/16
摘要： A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from the main memory unit, and a cache control unit that controls forwarding of circuit configuration information from the cache unit to the processing element. The cache control unit selects circuit configuration information which must be forwarded to each processing element. When the selected circuit configuration information is not stored in the cache unit, the cache control unit reads out the circuit configuration information from the main memory unit, stores the read-out circuit configuration information in the cache unit, and sends forward the circuit configuration information to the processing element from the cache unit.
摘要翻译：可重构装置包括多个处理元件，存储多条电路配置信息的主存储器单元，将从主存储器单元转发到至少一个处理元件的电路配置信息高速缓存的高速缓存单元，以及高速缓存控制控制电路配置信息从高速缓存单元转发到处理单元的单元。高速缓存控制单元选择必须转发给每个处理单元的电路配置信息。当所选择的电路配置信息未被存储在高速缓存单元中时，高速缓存控制单元从主存储器单元读出电路配置信息，将读出的电路配置信息存储在高速缓存单元中，并且发送电路配置信息从缓存单元到处理元件。

3. 发明授权

US07523292B2 Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix 有权
标题翻译：具有状态控制单元的阵列式处理器，其控制以矩阵形式布置的多个处理器元件
公开(公告)号：US07523292B2
公开(公告)日：2009-04-21
申请号：US10682830
申请日：2003-10-10
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.
摘要翻译：多个处理器元件分别按照已经被设置为数据并且相互连接关系被切换控制的指令代码单独执行数据处理，以矩阵形式排列，并且该多个处理器元件的指令代码被状态控制单元依次切换。状态控制单元由多个单元组成，这些单元相互通信以实现链接操作，并且多个处理器元件被分成与状态控制单元数量相对应的多个元件区域。多个状态控制单元被布置用于多个元件区域中的每一个，并且连接到处理器元件，由此多个状态控制单元可以单独地控制多个小规模状态转换，或者多个状态控制单元可以合作控制单一的大规模国家转型。

4. 发明授权

US08151089B2 Array-type processor having plural processor elements controlled by a state control unit 有权
标题翻译：具有由状态控制单元控制的多个处理器单元的阵列型处理器
公开(公告)号：US08151089B2
公开(公告)日：2012-04-03
申请号：US10694822
申请日：2003-10-29
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.
摘要翻译：排列成行和列的多个处理器元件根据单独设置为数据并提供事件数据作为输出的指令代码单独执行数据处理。状态控制单元由多个单元组成，多个单元根据计算机程序和事件数据连续地切换多个处理器单元的指令代码，这些状态控制单元相互通信以根据需要实现链接操作。事件分配装置将事件数据分配给相互通信的多个状态控制单元，以实现链接操作，由此多个状态控制单元可以实现链接操作以控制大规模状态转换。

5. 发明授权

US07120903B2 Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus 有权
标题翻译：用于生成用于并行操作装置的对象程序的数据的数据处理装置和方法
公开(公告)号：US07120903B2
公开(公告)日：2006-10-10
申请号：US10252564
申请日：2002-09-24
申请人： Takao Toi , Toru Awashima , Yoshiyuki Miyazawa , Noritsugu Nakamura , Taro Fujii , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Toru Awashima , Yoshiyuki Miyazawa , Noritsugu Nakamura , Taro Fujii , Koichiro Furuta , Masato Motomura
IPC分类号： G06F9/45 , G06F15/00 , G06F7/38 , G06F15/76 , G06F9/46
CPC分类号： G06F17/5045
摘要： An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.
摘要翻译：根据描述并行操作装置的操作的通用源代码，生成用于顺序切换并行操作装置中矩阵排列的处理电路的上下文的目标代码。根据并行操作装置的操作的源代码，根据预先登记的表示并行运算装置的物理结构等的限制条件生成数据流图（DFG），并将其调度到控制数据流图（CDFG）。从CDFG生成寄存器传送级别（RTL）描述，将有限状态机转换为目标代码，并将数据路径转换为网络列表。在每个上下文中，从网络列表生成处理电路的目标代码。

6. 发明授权

US07647485B2 Data processing system for debugging utilizing halts in a parallel device 有权
标题翻译：数据处理系统，用于并行设备中的停止调试
公开(公告)号：US07647485B2
公开(公告)日：2010-01-12
申请号：US10927377
申请日：2004-08-27
申请人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
发明人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
IPC分类号： G06F9/00
CPC分类号： G06F11/3624 , G06F11/3632
摘要： A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.
摘要翻译：一种用于并行运算装置调试码的数据处理装置，包括以矩阵形式布置的多个数据处理电路，并且根据目标代码使每个操作周期的操作状态的连续转换包括：操作执行装置，用于引起所述并行算术装置通过所述目标代码执行状态转换; 设备停止装置，用于暂时停止每个操作周期的状态转换; 结果输出装置，用于读取和提供停止的并行运算装置的多个数据处理电路的保持数据，连接关系和操作命令的至少一部分的输出; 恢复输入装置，用于接收状态转换的恢复命令作为输入; 以及操作恢复装置，用于使得操作执行装置在输入恢复命令时恢复状态转换。

7. 发明申请

US20050050522A1 Data processing system 有权
标题翻译：数据处理系统
公开(公告)号：US20050050522A1
公开(公告)日：2005-03-03
申请号：US10927377
申请日：2004-08-27
申请人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
发明人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
IPC分类号： G06F11/28 , G06F15/76 , G06F15/80
CPC分类号： G06F11/3624 , G06F11/3632
摘要： A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.
摘要翻译：一种用于并行运算装置调试码的数据处理装置，包括以矩阵形式布置的多个数据处理电路，并且根据目标代码使每个操作周期的操作状态的连续转换包括：操作执行装置，用于引起所述并行算术装置通过所述目标代码执行状态转换; 设备停止装置，用于暂时停止每个操作周期的状态转换; 结果输出装置，用于读取和提供停止的并行运算装置的多个数据处理电路的保持数据，连接关系和操作命令的至少一部分的输出; 恢复输入装置，用于接收状态转换的恢复命令作为输入; 以及操作恢复装置，用于使得操作执行装置在输入恢复命令时恢复状态转换。

8. 发明授权

US07793092B2 Information processing apparatus and method for using reconfigurable device 有权
标题翻译：信息处理装置及其使用方法
公开(公告)号：US07793092B2
公开(公告)日：2010-09-07
申请号：US11616751
申请日：2006-12-27
申请人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
IPC分类号： G06F9/00 , G06F1/24 , G06F17/50 , G06F9/44
CPC分类号： G06F1/3218
摘要： Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.
摘要翻译：生成用于实现具有不同属性的多个电路的配置代码，并将其存储在用于在可重新配置设备中执行的每个任务的存储器中。当可重构设备被操作时，根据来自具有不同属性的多个电路中的系统的操作状态来选择要由可重新配置设备执行的适当电路，并且用于实现所选择的电路的配置代码从内存进入可重新配置的设备。

9. 发明申请

US20070150718A1 INFORMATION PROCESSING APPARATUS AND METHOD FOR USING RECONFIGURABLE DEVICE 有权
标题翻译：信息处理装置和使用可重新配置的装置的方法
公开(公告)号：US20070150718A1
公开(公告)日：2007-06-28
申请号：US11616751
申请日：2006-12-27
申请人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
IPC分类号： G06F1/24
CPC分类号： G06F1/3218
摘要： Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.
摘要翻译：生成用于实现具有不同属性的多个电路的配置代码，并将其存储在用于在可重新配置设备中执行的每个任务的存储器中。当可重构设备被操作时，根据来自具有不同属性的多个电路中的系统的操作状态来选择要由可重新配置设备执行的适当电路，并且用于实现所选择的电路的配置代码从内存进入可重新配置的设备。

10. 发明授权

US06281703B1 Programmable device with an array of programmable cells and interconnection network 有权
标题翻译：具有可编程单元阵列和互连网络的可编程器件
公开(公告)号：US06281703B1
公开(公告)日：2001-08-28
申请号：US09493154
申请日：2000-01-28
申请人： Koichiro Furuta , Taro Fujii , Masato Motomura
发明人： Koichiro Furuta , Taro Fujii , Masato Motomura
IPC分类号： H03K19177
CPC分类号： H03K19/17756 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： The present invention provide a programmable device comprising: an array of plural programmable cells; a first sub-interconnection network comprising a plurality of first interconnections which extend to surround each of the plural programmable cells for transmitting data; and a second sub-interconnection network comprising a plurality of second interconnections which extend to surround each of the plural programmable cells for transmitting control informations, so that each of the plural programmable cells selects one of plural configuable informations stored therein in accordance with the control information supplied from the second sub-interconnection network.
摘要翻译：本发明提供一种可编程装置，包括：多个可编程单元阵列; 第一子互连网络，包括多个第一互连，其延伸以包围所述多个可编程单元中的每一个以发送数据; 以及第二子互连网络，其包括多个第二互连，其延伸以包围所述多个可编程单元中的每一个以发送控制信息，使得所述多个可编程单元中的每一个根据所述控制信息选择存储在其中的多个可配置信息中的一个从第二子互连网络提供。

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