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1. 发明申请

US20090249262A1 BEHAVIORAL SYNTHESIS DEVICE, BEHAVIORAL SYNTHESIS METHOD, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：行为综合设备，行为综合方法和计算机程序产品
公开(公告)号：US20090249262A1
公开(公告)日：2009-10-01
申请号：US12409856
申请日：2009-03-24
申请人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
发明人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.
摘要翻译：行为综合装置包括：简档单元，其基于由行为合成单元生成的第一寄存器传送级别描述，在可重新配置的硬件上实现电子电路，致动所实现的电子电路，并且使电路从致动的电路输出简档信息电子电路; 以及优化器，其基于所述简档单元使所述电路输出的所述简档信息，生成用于优化由所述行为综合单元执行的行为综合的优化信息，并将所生成的优化信息输出到所述行为综合单元，其中，合成单元获取第一行为级别描述，并且将所获取的第一行为级别描述进行行为综合，并且基于优化器输出的优化信息生成第二寄存器传送级别描述。

2. 发明授权

US08516414B2 Behavioral synthesis device, behavioral synthesis method, and computer program product 有权
标题翻译：行为综合装置，行为综合方法和计算机程序产品
公开(公告)号：US08516414B2
公开(公告)日：2013-08-20
申请号：US12409856
申请日：2009-03-24
申请人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
发明人： Yoshinosuke Kato , Takao Toi , Noritsugu Nakamura , Toru Awashima , Hirokazu Kami
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.
摘要翻译：行为综合装置包括：简档单元，其基于由行为合成单元生成的第一寄存器传送级别描述，在可重新配置的硬件上实现电子电路，致动所实现的电子电路，并且使电路从致动的电路输出简档信息电子电路; 以及优化器，其基于所述简档单元使所述电路输出的所述简档信息，生成用于优化由所述行为综合单元执行的行为综合的优化信息，并将所生成的优化信息输出到所述行为综合单元，其中，合成单元获取第一行为级别描述，并且将所获取的第一行为级别描述进行行为综合，并且基于优化器输出的优化信息生成第二寄存器传送级别描述。

3. 发明申请

US20080040700A1 Behavioral synthesizer, debugger, writing device and computer aided design system and method 审中-公开
标题翻译：行为综合器，调试器，书写装置和计算机辅助设计系统及方法
公开(公告)号：US20080040700A1
公开(公告)日：2008-02-14
申请号：US11727948
申请日：2007-03-29
申请人： Yoshinosuke Katoh , Toru Awashima , Noritsugu Nakamura , Hirokazu Kami , Takao Toi
发明人： Yoshinosuke Katoh , Toru Awashima , Noritsugu Nakamura , Hirokazu Kami , Takao Toi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for processing at a logic synthesizing stage, placement and routing stage, debugging stage, writing stage of circuit information to a reconfigurable device, or the like, so as to use storage elements that are to be allocated to the variables described in the behavioral level description in common and to achieve optimization such as minimizing data paths and the like. Also in a debugger and in a writing device for writing circuit information, the aforementioned liveness information is used to execute a task of not displaying invalid variables, a task of reducing the amount of information to be saved to an external memory, etc.
摘要翻译：从行为综合获得的活动信息，并且显示了在行为级别描述中描述的变量具有有效值的时期，用于逻辑合成阶段，布局和路由阶段，调试阶段，电路信息写入阶段的处理可重新配置的设备等，以便使用要分配给行为级别描述中描述的变量的存储元件，并且实现最小化数据路径等的优化。另外，在调试器和用于写入电路信息的写入装置中，上述活动信息用于执行不显示无效变量的任务，减少要保存到外部存储器的信息量的任务等。

4. 发明授权

US07647485B2 Data processing system for debugging utilizing halts in a parallel device 有权
标题翻译：数据处理系统，用于并行设备中的停止调试
公开(公告)号：US07647485B2
公开(公告)日：2010-01-12
申请号：US10927377
申请日：2004-08-27
申请人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
发明人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
IPC分类号： G06F9/00
CPC分类号： G06F11/3624 , G06F11/3632
摘要： A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.
摘要翻译：一种用于并行运算装置调试码的数据处理装置，包括以矩阵形式布置的多个数据处理电路，并且根据目标代码使每个操作周期的操作状态的连续转换包括：操作执行装置，用于引起所述并行算术装置通过所述目标代码执行状态转换; 设备停止装置，用于暂时停止每个操作周期的状态转换; 结果输出装置，用于读取和提供停止的并行运算装置的多个数据处理电路的保持数据，连接关系和操作命令的至少一部分的输出; 恢复输入装置，用于接收状态转换的恢复命令作为输入; 以及操作恢复装置，用于使得操作执行装置在输入恢复命令时恢复状态转换。

5. 发明申请

US20050050522A1 Data processing system 有权
标题翻译：数据处理系统
公开(公告)号：US20050050522A1
公开(公告)日：2005-03-03
申请号：US10927377
申请日：2004-08-27
申请人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
发明人： Hirokazu Kami , Takao Toi , Toru Awashima , Kenichiro Anjo , Koichiro Furuta , Taro Fujii , Masato Motomura
IPC分类号： G06F11/28 , G06F15/76 , G06F15/80
CPC分类号： G06F11/3624 , G06F11/3632
摘要： A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.
摘要翻译：一种用于并行运算装置调试码的数据处理装置，包括以矩阵形式布置的多个数据处理电路，并且根据目标代码使每个操作周期的操作状态的连续转换包括：操作执行装置，用于引起所述并行算术装置通过所述目标代码执行状态转换; 设备停止装置，用于暂时停止每个操作周期的状态转换; 结果输出装置，用于读取和提供停止的并行运算装置的多个数据处理电路的保持数据，连接关系和操作命令的至少一部分的输出; 恢复输入装置，用于接收状态转换的恢复命令作为输入; 以及操作恢复装置，用于使得操作执行装置在输入恢复命令时恢复状态转换。

6. 发明授权

US07793092B2 Information processing apparatus and method for using reconfigurable device 有权
标题翻译：信息处理装置及其使用方法
公开(公告)号：US07793092B2
公开(公告)日：2010-09-07
申请号：US11616751
申请日：2006-12-27
申请人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
IPC分类号： G06F9/00 , G06F1/24 , G06F17/50 , G06F9/44
CPC分类号： G06F1/3218
摘要： Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.
摘要翻译：生成用于实现具有不同属性的多个电路的配置代码，并将其存储在用于在可重新配置设备中执行的每个任务的存储器中。当可重构设备被操作时，根据来自具有不同属性的多个电路中的系统的操作状态来选择要由可重新配置设备执行的适当电路，并且用于实现所选择的电路的配置代码从内存进入可重新配置的设备。

7. 发明申请

US20070150718A1 INFORMATION PROCESSING APPARATUS AND METHOD FOR USING RECONFIGURABLE DEVICE 有权
标题翻译：信息处理装置和使用可重新配置的装置的方法
公开(公告)号：US20070150718A1
公开(公告)日：2007-06-28
申请号：US11616751
申请日：2006-12-27
申请人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
发明人： Takao Toi , Tooru Awashima , Hirokazu Kami , Takeshi Inuo , Nobuki Kajihara , Taro Fujii , Kenichiro Anjo , Koichiro Furuta , Masato Motomura
IPC分类号： G06F1/24
CPC分类号： G06F1/3218
摘要： Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.
摘要翻译：生成用于实现具有不同属性的多个电路的配置代码，并将其存储在用于在可重新配置设备中执行的每个任务的存储器中。当可重构设备被操作时，根据来自具有不同属性的多个电路中的系统的操作状态来选择要由可重新配置设备执行的适当电路，并且用于实现所选择的电路的配置代码从内存进入可重新配置的设备。

8. 发明申请

US20050172103A1 Array-type computer processor 有权
标题翻译：阵列型计算机处理器
公开(公告)号：US20050172103A1
公开(公告)日：2005-08-04
申请号：US11049305
申请日：2005-02-03
申请人： Takeshi Inuo , Nobuki Kajihara , Takao Toi , Tooru Awashima , Hirokazu Kami , Taro Fujii , Kenichiro Anjo , Kouichiro Furuta , Masato Motomura
发明人： Takeshi Inuo , Nobuki Kajihara , Takao Toi , Tooru Awashima , Hirokazu Kami , Taro Fujii , Kenichiro Anjo , Kouichiro Furuta , Masato Motomura
IPC分类号： G06F15/80 , G06F15/00
CPC分类号： G06F15/8023 , G06F9/30036 , G06F9/3879 , G06F9/3887
摘要： An array-type computer processor obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes, from an external program memory which stores data of a computer program. Every time the operations with the temporarily-held instruction codes are complete, the subsequent instruction codes are data obtained, so that the operation according to a computer program can be performed even if the data volume of the computer program is over the storage capacity.
摘要翻译：阵列型计算机处理器从存储计算机程序的数据的外部程序存储器中获取预定数量的协同部分指令代码的数据，并且暂时保持预定数量的数据获取的指令代码进行操作。每当具有暂时保持的指令代码的操作完成时，后续指令代码是获得的数据，使得即使计算机程序的数据量超过存储容量，也可以执行根据计算机程序的操作。

9. 发明授权

US07650484B2 Array—type computer processor with reduced instruction storage 有权
标题翻译：阵列式计算机处理器，减少指令存储
公开(公告)号：US07650484B2
公开(公告)日：2010-01-19
申请号：US11049305
申请日：2005-02-03
申请人： Takeshi Inuo , Nobuki Kajihara , Takao Toi , Tooru Awashima , Hirokazu Kami , Taro Fujii , Kenichiro Anjo , Kouichiro Furuta , Masato Motomura
发明人： Takeshi Inuo , Nobuki Kajihara , Takao Toi , Tooru Awashima , Hirokazu Kami , Taro Fujii , Kenichiro Anjo , Kouichiro Furuta , Masato Motomura
IPC分类号： G06F7/00
CPC分类号： G06F15/8023 , G06F9/30036 , G06F9/3879 , G06F9/3887
摘要： An array-type computer processor including a data path unit communicating with a state control unit obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes comprising cooperative partial instruction codes corresponding to contexts and operation states for the data path unit and the state control unit, respectively, from an external program memory which stores data of a computer program. Every time the operations with the temporarily-held instruction codes, including the corresponding cooperative partial instruction codes, are complete, in accordance with event data entered in the state control unit, the subsequent instruction codes are data obtained as cooperative partial instruction codes respectively corresponding to contexts and operating states, so that the operation according to a computer program can be performed even if the data volume of the computer program is over the storage capacity of the data path unit and the state control unit.
摘要翻译：包括与状态控制单元通信的数据路径单元的阵列式计算机处理器获得预定数量的协同部分指令代码的数据，并且暂时保持包含协调部分指令代码对应的预定数量的数据获取指令代码分别用于存储计算机程序的数据的外部程序存储器的数据路径单元和状态控制单元的上下文和操作状态。每当具有临时保持的指令代码的操作（包括相应的协同部分指令代码）完成时，根据输入到状态控制单元中的事件数据，后续指令代码是分别对应于上下文和操作状态，使得即使计算机程序的数据量超过数据路径单元和状态控制单元的存储容量，也可以执行根据计算机程序的操作。

10. 发明授权

US07287146B2 Array-type computer processor 有权
标题翻译：阵列型计算机处理器
公开(公告)号：US07287146B2
公开(公告)日：2007-10-23
申请号：US11048071
申请日：2005-02-02
申请人： Takeshi Inuo , Nobuki Kajihara , Takao Toi , Tooru Awashima , Hirokazu Kami , Taro Fujii , Kenichiro Anjo , Kouichiro Furuta , Masato Motomura
发明人： Takeshi Inuo , Nobuki Kajihara , Takao Toi , Tooru Awashima , Hirokazu Kami , Taro Fujii , Kenichiro Anjo , Kouichiro Furuta , Masato Motomura
IPC分类号： G06F7/00
CPC分类号： G06F15/8023 , G06F15/7867
摘要： An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when stopped, and temporarily holds them for each of a plurality of the computer programs. Upon completion of this, the array-type computer processor reads the operation state and processed data of any other computer program and sets them in the state control unit and data-path unit. Upon completion of this, the array-type computer processor outputs to the state control unit the event data for starting the operation. The state control unit then starts to sequentially transfer the operation state, thereby making it possible to perform the process operations according to a plurality of computer programs in a time-sharing manner.
摘要翻译：当输入用于任务切换的事件数据时，阵列式计算机处理器停止，多个计算机程序保持状态控制单元和数据路径单元。阵列型计算机处理器在停止时获取状态控制单元的操作状态和数据路径单元的处理数据，并且为多个计算机程序中的每一个暂时保存它们。完成后，阵列型计算机处理器读取任何其他计算机程序的操作状态和处理数据，并将其设置在状态控制单元和数据路径单元中。完成后，阵列型计算机处理器向状态控制单元输出用于开始操作的事件数据。状态控制单元然后开始顺序地传送操作状态，从而使得可以以分时方式执行根据多个计算机程序的处理操作。

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