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1. 发明授权

US06570194B2 Compound semiconductor field effect transistor with improved ohmic contact layer structure and method of forming the same 失效
标题翻译：具有改善的欧姆接触层结构的复合半导体场效应晶体管及其形成方法
公开(公告)号：US06570194B2
公开(公告)日：2003-05-27
申请号：US09793656
申请日：2001-02-27
申请人： Takehiko Kato , Naotaka Iwata
发明人： Takehiko Kato , Naotaka Iwata
IPC分类号： H01L310328
CPC分类号： H01L29/452 , H01L29/4175 , H01L29/7785
摘要： The present invention provides a structure of a semiconductor device, the structure comprising: a compound semiconductor multi-layer structure having at least a channel region; and at least an ohmic contact layer provided adjacent to a first side face of the multi-layer structure, and the ohmic contact layer being in contact with at least a part of the first side face, wherein the ohmic contact layer has a top extending portion which extends in contact with a part of a top surface of the multi-layer structure.
摘要翻译：本发明提供一种半导体器件的结构，该结构包括：至少具有沟道区的化合物半导体多层结构; 以及至少与所述多层结构的第一侧面相邻设置的欧姆接触层，所述欧姆接触层与所述第一侧面的至少一部分接触，其中所述欧姆接触层具有顶部延伸部分其与多层结构的顶表面的一部分延伸接触。

2. 发明授权

US06534790B2 Compound semiconductor field effect transistor 有权
标题翻译：复合半导体场效应晶体管
公开(公告)号：US06534790B2
公开(公告)日：2003-03-18
申请号：US09796803
申请日：2001-03-02
申请人： Takehiko Kato , Kazuki Ota , Hironobu Miyamoto , Naotaka Iwata , Masaaki Kuzuhara
发明人： Takehiko Kato , Kazuki Ota , Hironobu Miyamoto , Naotaka Iwata , Masaaki Kuzuhara
IPC分类号： H01L2915
CPC分类号： H01L29/66462 , H01L29/7785
摘要： The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.
摘要翻译：本发明提供一种在半绝缘化合物半导体衬底上具有缓冲层的场效应晶体管（FET）包括由第一导电型外延生长层（例如InGaAs）制成的沟道层的有源层; 源极/漏极，形成在形成在所述有源层上或其侧面上的第一导电型接触层上; 由第二导电型外延生长层（例如p + -GaAs）制成的栅极层; 以及形成在所述栅极层上的栅电极; 在所述第二导电型栅极层和所述沟道层之间还具有快速降低从所述栅极层扩散到所述沟道层的能带的能量的半导体层（例如InGaP）。本发明提高了在栅极区（JFET）中具有pn结的FET的耐压特性，并且实现了JFET的稳定操作。

3. 发明授权

US06552373B2 Hetero-junction field effect transistor having an intermediate layer 有权
标题翻译：具有中间层的异质结场效应晶体管
公开(公告)号：US06552373B2
公开(公告)日：2003-04-22
申请号：US09818587
申请日：2001-03-28
申请人： Yuji Ando , Hironobu Miyamoto , Naotaka Iwata , Koji Matsunaga , Masaaki Kuzuhara , Kensuke Kasahara , Kazuaki Kunihiro , Yuji Takahashi , Tatsuo Nakayama , Nobuyuki Hayama , Yasuo Ohno
发明人： Yuji Ando , Hironobu Miyamoto , Naotaka Iwata , Koji Matsunaga , Masaaki Kuzuhara , Kensuke Kasahara , Kazuaki Kunihiro , Yuji Takahashi , Tatsuo Nakayama , Nobuyuki Hayama , Yasuo Ohno
IPC分类号： H01L31072
CPC分类号： H01L29/7787 , H01L29/2003
摘要： A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.
摘要翻译：异质结FET在电子供给层和n型盖层之间具有包括n型杂质掺杂层的中间层。中间层通过离子化的正电荷抵消在电子供给层和n型覆盖层之间产生的极化的负电荷，从而减少对电子的阻挡和源极/漏极电阻。

4. 发明授权

US5943577A Method of making heterojunction bipolar structure having air and implanted isolations 失效
标题翻译：具有空气和植入隔离物的异质结双极结构的方法
公开(公告)号：US5943577A
公开(公告)日：1999-08-24
申请号：US982309
申请日：1997-12-01
申请人： Walter Contrata , Naotaka Iwata
发明人： Walter Contrata , Naotaka Iwata
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L27/095 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L21/7605 , Y10S148/072
摘要： In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across the semiconductor device to electrically connect the semiconductor device with an adjacent semiconductor device. Subsequently, the device forming region is etched on the condition that the conducting path is left. Finally, the conducting path is disrupted after the etching process. Thus, the semiconductor device and the adjacent semiconductor device are left in an electrical contact via the conducting path during the etching process. Consequently, the uniformity of the etching between the semiconductor devices is largely improved.
摘要翻译：在制造半导体器件的方法中，在衬底上形成具有器件形成区域的半导体层。接下来，除了器件形成区域之外的区域变为绝缘体。在这种情况下，在半导体器件上留下导电路径以将半导体器件与相邻的半导体器件电连接。随后，在导电路径被留下的条件下蚀刻器件形成区域。最后，蚀刻工艺后导电路径被破坏。因此，在蚀刻过程期间，半导体器件和相邻的半导体器件经由导电路径留在电接触中。因此，半导体器件之间的蚀刻的均匀性大大提高。

5. 发明授权

US06388530B1 Microwave amplifier implemented by heterojunction field effect transistors 失效
标题翻译：微波放大器由异质结场效应晶体管实现
公开(公告)号：US06388530B1
公开(公告)日：2002-05-14
申请号：US09473924
申请日：1999-12-28
申请人： Takeshi Nishimura , Naotaka Iwata
发明人： Takeshi Nishimura , Naotaka Iwata
IPC分类号： H03F304
CPC分类号： H03F1/0244 , H03F1/0261
摘要： A microwave amplifier circuit controls the output power thereof depending upon an associated transmitter of a wireless telephone, and a main amplifier transistor and switching transistors of a drain bias controlling circuit are implemented by gallium-arsenide heterojunction field effect transistors so that, even if they are integrated on a single compound semiconductor substrate, the microwave amplifier circuit achieves a high power efficiency over a wide output voltage range.
摘要翻译：微波放大器电路根据无线电话的相关发射机控制其输出功率，并且主放大器晶体管和漏极偏置控制电路的开关晶体管由砷化镓异质结场效应晶体管实现，使得即使它们是集成在单个化合物半导体衬底上，微波放大器电路在宽输出电压范围内实现高功率效率。

6. 发明授权

US06624440B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06624440B2
公开(公告)日：2003-09-23
申请号：US10021540
申请日：2001-10-30
申请人： Yasunori Bito , Naotaka Iwata
发明人： Yasunori Bito , Naotaka Iwata
IPC分类号： H01L2906
CPC分类号： H01L29/66462 , H01L29/0891 , H01L29/7783
摘要： An FET (Field Effect Transistor) has an epitaxial wafer including an Al0.2Ga0.8As gate contact layer. A GaAs gate buried layer doped with Si, Al0.2Ga0.8As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 &OHgr;·mm is achievable which is lower than the conventional ON resistance by 0.2 &OHgr;·mm.
摘要翻译： FET（场效应晶体管）具有包括Al 0.2 Ga 0.8 As栅极接触层的外延晶片。通过外延生长，在栅极接触层上依次形成掺杂有Si，Al0.2Ga0.8As宽凹槽停止层，掺杂有Si的未掺杂GaAs层和GaAs覆盖层的GaAs栅极掩埋层。在未掺杂的GaAs层上形成电子聚集层并减少势垒。这允许电子以较高的概率穿过AlGaAs层的势垒。由于GaAs层不掺杂杂质，所以电子散射很小，实现较高的迁移率。因此可以降低从盖层到沟道层的接触电阻。此外，由于栅极接触层不暴露于外部，薄层电阻微小地增加。可以实现低至1.4Ω·μm的导通电阻，其低于传统的ON电阻0.2Ω·mm。

7. 发明授权

US06436756B1 Semiconductor device and fabrication method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06436756B1
公开(公告)日：2002-08-20
申请号：US09187610
申请日：1998-11-06
申请人： Takeshi B. Nishimura , Naotaka Iwata
发明人： Takeshi B. Nishimura , Naotaka Iwata
IPC分类号： H01L218242
CPC分类号： H01L27/0688
摘要： In order to form a first capacitor having a small capacitance and a second capacitor having a large capacitance on a substance with a minimum number of manufacturing steps, at least one of electrodes of the first capacitor and at least one of electrodes of the second capacitor are formed simultaneously.
摘要翻译：为了在具有最小数量的制造步骤的物质上形成具有小电容的第一电容器和具有大电容的第二电容器，第一电容器的电极和第二电容器的至少一个电极中的至少一个是同时形成。

8. 发明授权

US6144051A Semiconductor device having a metal-insulator-metal capacitor 失效
标题翻译：具有金属 - 绝缘体 - 金属电容器的半导体器件
公开(公告)号：US6144051A
公开(公告)日：2000-11-07
申请号：US87159
申请日：1998-05-29
申请人： Takeshi B Nishimura , Naotaka Iwata
发明人： Takeshi B Nishimura , Naotaka Iwata
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/02
CPC分类号： H01L28/55
摘要： A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor comprises the steps of forming a first dielectric film on a substrate, forming a MIM capacitor on the first dielectric film, forming a second dielectric film covering the MIM capacitor, selectively removing the first and second dielectric films to expose the substrate surface, surface treating using a hydrochloric acid solution, forming a third dielectric film on the second dielectric film and the substrate, and forming a transistor on the third dielectric film. The second dielectric film protects the capacitor insulator film of the MIM capacitor.
摘要翻译：一种制造具有金属 - 绝缘体 - 金属（MIM）电容器的半导体器件的方法包括以下步骤：在衬底上形成第一电介质膜，在第一电介质膜上形成MIM电容器，形成覆盖MIM电容器的第二电介质膜选择性地去除第一和第二介电膜以露出衬底表面，使用盐酸溶液进行表面处理，在第二电介质膜和衬底上形成第三电介质膜，并在第三电介质膜上形成晶体管。第二介质膜保护MIM电容器的电容绝缘膜。

9. 发明授权

US6072205A Passive element circuit 失效
标题翻译：被动元件电路
公开(公告)号：US6072205A
公开(公告)日：2000-06-06
申请号：US090533
申请日：1998-06-04
申请人： Keiko Yamaguchi , Naotaka Iwata
发明人： Keiko Yamaguchi , Naotaka Iwata
IPC分类号： H01L27/04 , H01L21/822 , H01L27/01 , H01L29/80 , H01L31/112
CPC分类号： H01L27/01 , H01L2224/45144 , H01L2224/48091 , H01L2924/30107 , H01L2924/3011
摘要： A passive element circuit is formed by a spiral inductor, a high-dielectric-constant thin-film capacitor, a via hole, and a bonding pad. By using SrTiO.sub.3 as the high-dielectric-constant thin-film, which exhibits a dielectric constant of 200 up to a frequency of 20 GHz, it is possible to achieve a reduction of the capacitor surface area to approximately 1/30 of the area formerly required when using a SiN.sub.x (dielectric constant up to 6.5). Two high-dielectric-constant thin-film capacitors, a via hole for grounding, and a bonding pad are disposed at the center, which are surrounded by the spiral inductor. To connect the two high-dielectric-constant thin-film capacitors are joined in series, they are formed on one high-dielectric-constant thin-film. A lead from the spiral inductor is made by a metal wire from the bonding pad at the center.
摘要翻译：无源元件电路由螺旋电感器，高介电常数薄膜电容器，通孔和接合焊盘构成。通过使用SrTiO3作为介电常数为200的高介电常数薄膜，直到20GHz的频率，可以使电容器表面积减小到大约+ E，从而使1/30 +使用SiNx（介电常数高达6.5）以前要求的区域。两个高介电常数薄膜电容器，一个用于接地的通孔和一个接合焊盘设置在中心，被螺旋电感器包围。为了连接两个高介电常数薄膜电容器串联连接，它们形成在一个高介电常数的薄膜上。来自螺旋电感器的引线由来自中心的焊盘的金属线制成。

10. 发明授权

US4689646A Depletion mode two-dimensional electron gas field effect transistor and the method for manufacturing the same 失效
标题翻译：耗散模式二维电子气场效应晶体管及其制造方法
公开(公告)号：US4689646A
公开(公告)日：1987-08-25
申请号：US741597
申请日：1985-06-05
申请人： Yoshishige Matsumoto , Naotaka Iwata
发明人： Yoshishige Matsumoto , Naotaka Iwata
IPC分类号： H01L29/812 , H01L21/20 , H01L21/268 , H01L21/324 , H01L21/338 , H01L29/04 , H01L29/15 , H01L29/778 , H01L29/80
CPC分类号： H01L21/268 , H01L29/04 , H01L29/155 , H01L29/7787
摘要： The depletion mode two-dimensional electron gas field effect transistor comprises a substantially pure semiconductor layer, an impurity doped super lattice semiconductor layer formed on the pure semiconductor layer, the energy band gaps and the electron affinities of the pure semiconductor layer and the super lattice semiconductor layer being selected to produce the two-dimensional electron gas at the surface of the pure semiconductor layer when no bias is applied to the super lattice semiconductor layer, source and drain regions formed separatedly in the super lattice semiconductor layer to reach the pure semiconductor layer, a gate electrode formed on the super lattice semiconductor layer between the source and drain regions, and large energy band gap regions formed at side portions of the gate electrode which do not face the source and drain regions, the large energy band gap regions having an energy band gap larger than the super lattice semiconductor layer and being formed by local annealing to convert the super lattice semiconductor to a mixed semiconductor.
摘要翻译：耗尽型二维电子气体场效应晶体管包括基本上纯的半导体层，形成在纯半导体层上的杂质掺杂超晶格半导体层，纯半导体层和超晶格半导体的能带隙和电子亲和力当在超晶格半导体层中分离形成的超晶格半导体层，源极和漏极区域不施加偏压以到达纯半导体层时，选择在纯半导体层的表面处产生二维电子气的层，形成在源极和漏极区域之间的超晶格半导体层上的栅电极，以及形成在栅电极的不面向源区和漏区的侧部的大能带隙区，大能带隙区具有能量带隙大于超晶格半导体层并由本地形成 l退火以将超晶格半导体转换成混合半导体。

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