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1. 发明授权

US6025613A Semiconductor device capable of reducing leak current and having excellent pinch-off characteristic and method of manufacturing the same 失效
标题翻译：能够减少漏电流并具有优异的夹断特性的半导体装置及其制造方法
公开(公告)号：US6025613A
公开(公告)日：2000-02-15
申请号：US22384
申请日：1998-02-12
申请人： Yasunori Bito , Naotaka Iwata
发明人： Yasunori Bito , Naotaka Iwata
IPC分类号： H01L21/302 , H01L21/318 , H01L21/335 , H01L21/338 , H01L29/812 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66863 , H01L29/66462
摘要： In a method of manufacturing a semiconductor device, the InP substrate is subjected to a NH.sub.3 plasma processing by a plasma CVD apparatus into which NH.sub.3 gas is introduced. The InP oxide film is deoxided and removed therefrom and an InN (nitride) film is then formed thereon. S.sub.i H.sub.3 gas and NH.sub.3 gas are introduced into the plasma CVD apparatus to form a SiNx spacer layer on the InN (nitride) film. A source electrode and drain electrode are formed as ohmic electrodes. A Pt layer is stacked on the InP channel region by evaporation lift-off or ion beam sputter method to form a gate electrode. Thereafter, by a process similar to that of forming the SiNx/InN spacer layer, a SiNx/InN passivation film is formed on all over the InP substrate including the source electrode, the drain electrode, and the gate electrode. Accordingly, a semiconductor device protected by the passivation film is completed.
摘要翻译：在制造半导体器件的方法中，通过引入NH 3气体的等离子体CVD装置对InP衬底进行NH 3等离子体处理。将氧化铟膜脱氧除去，然后在其上形成InN（氮化物）膜。将SiH 3气体和NH 3气体引入到等离子体CVD装置中，以在InN（氮化物）膜上形成SiNx间隔层。源电极和漏电极形成为欧姆电极。通过蒸发剥离或离子束溅射法在InP沟道区上堆叠Pt层以形成栅电极。此后，通过与形成SiNx / InN间隔层的工艺类似的工艺，在包括源电极，漏电极和栅电极的InP衬底的整个周围形成SiNx / InN钝化膜。因此，完成了被钝化膜保护的半导体器件。

2. 发明授权

US06624440B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06624440B2
公开(公告)日：2003-09-23
申请号：US10021540
申请日：2001-10-30
申请人： Yasunori Bito , Naotaka Iwata
发明人： Yasunori Bito , Naotaka Iwata
IPC分类号： H01L2906
CPC分类号： H01L29/66462 , H01L29/0891 , H01L29/7783
摘要： An FET (Field Effect Transistor) has an epitaxial wafer including an Al0.2Ga0.8As gate contact layer. A GaAs gate buried layer doped with Si, Al0.2Ga0.8As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 &OHgr;·mm is achievable which is lower than the conventional ON resistance by 0.2 &OHgr;·mm.
摘要翻译： FET（场效应晶体管）具有包括Al 0.2 Ga 0.8 As栅极接触层的外延晶片。通过外延生长，在栅极接触层上依次形成掺杂有Si，Al0.2Ga0.8As宽凹槽停止层，掺杂有Si的未掺杂GaAs层和GaAs覆盖层的GaAs栅极掩埋层。在未掺杂的GaAs层上形成电子聚集层并减少势垒。这允许电子以较高的概率穿过AlGaAs层的势垒。由于GaAs层不掺杂杂质，所以电子散射很小，实现较高的迁移率。因此可以降低从盖层到沟道层的接触电阻。此外，由于栅极接触层不暴露于外部，薄层电阻微小地增加。可以实现低至1.4Ω·μm的导通电阻，其低于传统的ON电阻0.2Ω·mm。

3. 发明授权

US08067788B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08067788B2
公开(公告)日：2011-11-29
申请号：US12061065
申请日：2008-04-02
申请人： Yasunori Bito
发明人： Yasunori Bito
IPC分类号： H01L31/072
CPC分类号： H01L29/7785 , H01L27/0605 , H01L29/0843 , H01L29/1066 , H01L29/205 , H01L29/432
摘要： A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer.
摘要翻译：半导体器件包括与第一场效应晶体管和第二场效应晶体管共同的衬底，形成在衬底上并与第一和第二场效应晶体管共同的第一导电类型的沟道层，形成的上部化合物半导体层在所述沟道层上并且与所述第一和第二场效应晶体管相同的第二导电类型的化合物半导体区域形成在与所述上部化合物半导体层相同的层中，所述第一场效应晶体管的栅电极与所述第二场效应晶体管欧姆接触化合物半导体区域和与上部化合物半导体层肖特基接触的第二场效应晶体管的栅电极。

4. 发明授权

US08421120B2 Field effect transistor capable of reducing shift of threshold voltage 有权
标题翻译：能够减小阈值电压偏移的场效应晶体管
公开(公告)号：US08421120B2
公开(公告)日：2013-04-16
申请号：US11760899
申请日：2007-06-11
申请人： Yasunori Bito
发明人： Yasunori Bito
IPC分类号： H01L29/66
CPC分类号： H01L29/7783
摘要： A problem is arisen in conventional J-FETs that a shifting in a threshold voltage (VT) is generated before or after an energization with a gate current. A junction gate field effect transistor (J-FET) according to the present invention includes an undoped InGaAs channel layer 5, which is capable of accumulating carrier of a first conductivity type, a p+ type GaAs layer 17 (semiconductor layer), which is provided on the undoped InGaAs channel layer 5, and contains an impurity of a second conductivity type, and a gate electrode 18, which is provided on the p+ type GaAs layer 17. Here, the concentration of hydrogen contained in the p+ type GaAs layer 17 is lower than the concentration of the second conductivity type carrier in the p+ type GaAs layer 17.
摘要翻译：在传统的J-FET中出现了在栅极电流通电之前或之后产生阈值电压（VT）偏移的问题。根据本发明的结栅场效应晶体管（J-FET）包括能够积聚第一导电类型的载流子的未掺杂的InGaAs沟道层5，提供的p +型GaAs层17（半导体层）在未掺杂的InGaAs沟道层5上，并且包含第二导电类型的杂质和设置在p +型GaAs层17上的栅电极18.这里，p +型GaAs层17中包含的氢的浓度为低于p +型GaAs层17中的第二导电类型载流子的浓度。

5. 发明授权

US08299499B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08299499B2
公开(公告)日：2012-10-30
申请号：US12632364
申请日：2009-12-07
申请人： Masayuki Aoike , Yasunori Bito
发明人： Masayuki Aoike , Yasunori Bito
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/20 , H01L29/201 , H01L29/42316 , H01L29/8128
摘要： A field effect transistor includes a Schottky layer; a stopper layer formed of InGaP and provided in a recess region on the Schottky layer; a cap layer provided on the stopper layer and formed of GaAs; and a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between the stopper layer and the cap layer. The cap layer includes a high concentration cap layer; and a low concentration cap layer provided directly or indirectly under the high concentration cap layer and having an impurity concentration lower than the high concentration cap layer.
摘要翻译：场效应晶体管包括肖特基层; 由InGaP形成的阻挡层，设置在肖特基层的凹部中; 盖层，设置在阻挡层上并由GaAs形成; 以及阻挡层上升抑制区域，被配置为抑制由阻挡层和盖层之间的界面电荷引起的势垒的上升。盖层包括高浓度盖层; 以及直接或间接地设置在高浓度盖层之下并且具有低于高浓度盖层的杂质浓度的低浓度盖层。

6. 发明授权

US08217424B2 Semiconductor device having stacked InGaP and GaAs layers, and method of making same 失效
标题翻译：具有堆叠的InGaP和GaAs层的半导体器件及其制造方法
公开(公告)号：US08217424B2
公开(公告)日：2012-07-10
申请号：US12549023
申请日：2009-08-27
申请人： Yasuyuki Yoshinaga , Yasunori Bito
发明人： Yasuyuki Yoshinaga , Yasunori Bito
IPC分类号： H01L29/778
CPC分类号： H01L29/7785 , H01L21/823456 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L27/0883 , H01L29/1066 , H01L29/205
摘要： It is desired for semiconductor devices to reduce leakage currents. In a semiconductor device having a stacked structure including a GaAs layer and an InGaP layer, p-type impurity is doped to the GaAs layer. Consequently, the conduction band of the GaAs is raised to higher than the Fermi level. As a result, electron accumulation is suppressed and the gate leakage current can be reduced.
摘要翻译：希望半导体器件减少泄漏电流。在具有GaAs层和InGaP层的层叠结构的半导体装置中，向GaAs层掺杂p型杂质。因此，GaAs的导带升高到高于费米能级。结果，抑制了电子积聚，并且可以降低栅极漏电流。

7. 发明授权

US07456444B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US07456444B2
公开(公告)日：2008-11-25
申请号：US11486127
申请日：2006-07-14
申请人： Yasunori Bito
发明人： Yasunori Bito
IPC分类号： H01L21/338
CPC分类号： H01L29/7785
摘要： A field effect transistor according to an embodiment of the invention includes: a semiconductor substrate; a channel layer of a first conductivity type formed on the semiconductor substrate; and a semiconductor layer of a second conductivity type that is buried in a recess structure formed in a semiconductor layer on the channel layer and connected with a gate electrode, in which the recess structure is formed using a recess stopper layer containing In, a semiconductor layer that contacts the bottom of the semiconductor layer of the second conductivity type does not contain In, and the uppermost semiconductor layer among semiconductor layers that contact a side surface of the semiconductor layer of the second conductivity type does not contain In.
摘要翻译：根据本发明实施例的场效应晶体管包括：半导体衬底; 形成在半导体衬底上的第一导电类型的沟道层; 以及第二导电类型的半导体层，其被埋在形成在沟道层上的半导体层中并与栅电极连接的凹陷结构中，其中使用包含In的凹陷阻挡层形成凹部结构，半导体层与第二导电类型的半导体层的底部接触的不含In的半导体层中的与半导体层的第二导电类型的侧面接触的最上层的半导体层不包含In。

8. 发明授权

US08253218B2 Protective element and semiconductor device 有权
标题翻译：保护元件和半导体器件
公开(公告)号：US08253218B2
公开(公告)日：2012-08-28
申请号：US13024033
申请日：2011-02-09
申请人： Yasunori Bito
发明人： Yasunori Bito
IPC分类号： H01L21/70
CPC分类号： H01L29/88 , H01L27/0288 , H01L27/0605 , H01L28/40
摘要： A semiconductor device includes at least one semiconductor element having a semiconductor stack containing a channel layer and a cap layer and a lower electrode and an upper electrode formed over a semiconductor stack, and at least one protective element having the semiconductor stack in common with the semiconductor element for protecting the semiconductor element. The protective element includes a recessed portion that penetrates the cap layer in the direction of the thickness, an insulation region formed in the semiconductor stack from the bottom of the recessed portion 221 in the direction of the thickness, and a pair of ohmic electrodes and formed on both sides of the recessed portion and connected to the cap layer.
摘要翻译：一种半导体器件包括至少一个半导体元件，该半导体元件具有包含沟道层和覆盖层的半导体堆叠，以及形成在半导体堆叠上的下电极和上电极，以及至少一个保护元件，其具有与半导体共同的半导体叠层用于保护半导体元件的元件。保护元件包括在厚度方向上贯穿盖层的凹部，在凹部221的底部沿厚度方向形成在半导体叠层中的绝缘区域和一对欧姆电极，并形成在凹部的两侧并与盖层连接。

9. 发明申请

US20120126288A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120126288A1
公开(公告)日：2012-05-24
申请号：US13317849
申请日：2011-10-31
申请人： Yasunori Bito
发明人： Yasunori Bito
IPC分类号： H01L27/06 , H01L21/28
CPC分类号： H01L27/0605 , H01L21/8252
摘要： A semiconductor device having first and second stacks formed successively over a common substrate, in which the first stack that remains after removing the second stack comprises a field effect transistor, the second stack that is stacked over the first stack comprises a device different from the field effect transistor, and the first stack comprising the field effect transistor has an etching stopper layer that defines a stopping position of a recess formed in the first stack and comprises InGaP, a lower compound semiconductor layer that is disposed below a gate electrode disposed in the recess and comprises AlGaAs, and a spacer layer that is interposed between the etching stopper layer and the lower compound semiconductor layer for preventing phosphorus contained in the etching stopper layer from thermally diffusing as far as the lower compound semiconductor layer and chemically bonding with constituents elements of the lower compound semiconductor layer.
摘要翻译：具有第一和第二堆叠的半导体器件连续地形成在公共衬底上，其中在去除第二堆叠之后保留的第一堆叠包括场效应晶体管，堆叠在第一堆叠上的第二堆叠包括不同于场的器件并且包括场效应晶体管的第一堆叠具有限定形成在第一堆叠中的凹部的停止位置的蚀刻停止层，并且包括InGaP，下部化合物半导体层，其设置在设置在凹部中的栅电极下方并且包括AlGaAs，以及间隔层，其被插入在蚀刻停止层和下部化合物半导体层之间，用于防止蚀刻停止层中所含的磷热扩散到下部化合物半导体层并化学键合低级化合物半导体层。

10. 发明授权

US08587027B2 Field effect transistor, method of manufacturing the same, and semiconductor device 有权
标题翻译：场效应晶体管，其制造方法以及半导体器件
公开(公告)号：US08587027B2
公开(公告)日：2013-11-19
申请号：US12457551
申请日：2009-06-15
申请人： Yasunori Bito
发明人： Yasunori Bito
IPC分类号： H01L21/318
CPC分类号： H01L29/7785 , H01L21/8252 , H01L27/0605
摘要： A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers 3 and 7, undoped AlGaAs spacer layers 4 and 6, and an undoped InGaAs channel layer 5) formed above a semi-insulating GaAs substrate, an upper semiconductor layer made up of at least one semiconductor layer and formed above the channel layer of the first conductivity type, a semiconductor layer of a second conductivity type (C-doped p+-GaAs layer 18) formed in a recess made in the upper semiconductor layer or formed above the upper semiconductor layer, a gate electrode placed above and in contact with the semiconductor layer of the second conductivity type, and a gate insulating film including a nitride film formed above and in contact with the upper semiconductor layer and an oxide film formed above the nitride film and having a larger thickness than the nitride film.
摘要翻译： J-FET包括形成在半导体层上方的第一导电类型的沟道层（Si掺杂的n型AlGaAs电子供体层3和7，未掺杂的AlGaAs间隔层4和6以及未掺杂的InGaAs沟道层5）绝缘GaAs衬底，由至少一个半导体层构成并形成在第一导电类型的沟道层上方的上半导体层，形成在凹部中的第二导电类型（C掺杂p + -GaAs层18）的半导体层在上半导体层中形成或形成在上半导体层上方的栅电极，设置在第二导电类型的半导体层的上方并与之接触的栅电极，以及包括在上半导体层上形成并与上半导体接触的栅极绝缘膜层和形成在氮化物膜上方并且具有比氮化物膜更大的厚度的氧化物膜。

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