专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5503901A Surface treatment method and surface treatment apparatus 失效
标题翻译：表面处理方法和表面处理装置
公开(公告)号：US5503901A
公开(公告)日：1996-04-02
申请号：US267799
申请日：1994-06-29
申请人： Takayuki Sakai , Hisataka Hayashi , Haruo Okano , Shigeyuki Takagi , Yutaka Uchida
发明人： Takayuki Sakai , Hisataka Hayashi , Haruo Okano , Shigeyuki Takagi , Yutaka Uchida
IPC分类号： H01L21/302 , C03C15/00 , H01L21/3065 , H01L21/311 , C03C15/02
CPC分类号： H01J37/32009 , C03C15/00 , H01J37/3233 , H01L21/31116 , H01J2237/3346
摘要： Etching selectivity is improved in a semiconductor process using a fluorocarbon gas. An energy incident to a substrate is controlled to have a value to cause transition from etching to deposition on a silicon nitride film, ions having (CF.sub.2).sub.n.sup.+ as a major component are guided onto the substrate to perform selective etching of a silicon oxide film against the silicon nitride film.
摘要翻译：在使用碳氟化合物气体的半导体工艺中，蚀刻选择性得到改善。控制入射到衬底的能量具有从蚀刻到沉积在氮化硅膜上的过渡的值，将具有（CF 2）n +作为主要成分的离子被引导到衬底上，以对氧化硅膜进行选择性蚀刻以反对氮化硅膜。

2. 发明授权

US5310454A Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US5310454A
公开(公告)日：1994-05-10
申请号：US26042
申请日：1993-03-04
申请人： Tokuhisa Ohiwa , Hisataka Hayashi , Keiji Horioka , Haruo Okano , Takaya Matsushita , Isahiro Hasegawa , Akira Takeuchi
发明人： Tokuhisa Ohiwa , Hisataka Hayashi , Keiji Horioka , Haruo Okano , Takaya Matsushita , Isahiro Hasegawa , Akira Takeuchi
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/31116
摘要： A dry etching method by a plasma etching forms a mask pattern, having an opening up to 1 .mu.m width on a silicon oxide layer formed on a silicon substrate. The substrate is laced into a reactive chamber having an etching gas introducing means and fluorocarbon gas and hydrogen gas as the etching gas are introduced such that a ratio of the hydrogen gas to the gas mixture satisfies 50% to 80%. The plasma is generated, and by using the plasma etching, the silicon oxide layer is etched according to the mask pattern to form an opening having an aspect ratio of more than 1 in the silicon oxide layer.
摘要翻译：通过等离子体蚀刻的干蚀刻方法形成在硅基板上形成的氧化硅层上具有至多1μm宽的开口的掩模图案。衬底被引入具有蚀刻气体引入装置的反应室和碳氟化合物气体和氢气作为蚀刻气体，使得氢气与气体混合物的比率满足50％至80％。产生等离子体，并且通过使用等离子体蚀刻，根据掩模图案蚀刻氧化硅层，以在氧化硅层中形成长径比大于1的开口。

3. 发明授权

US5445710A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5445710A
公开(公告)日：1995-08-29
申请号：US202372
申请日：1994-02-25
申请人： Masaru Hori , Hiroyuki Yano , Keiji Horioka , Hisataka Hayashi , Sadayuki Jimbo , Haruo Okano , Kazuhiro Tomioka , Yasuhiro Ito , Haruki Mori
发明人： Masaru Hori , Hiroyuki Yano , Keiji Horioka , Hisataka Hayashi , Sadayuki Jimbo , Haruo Okano , Kazuhiro Tomioka , Yasuhiro Ito , Haruki Mori
IPC分类号： H01L21/033 , H01L21/308 , H01L21/311 , H01L21/314 , H01L21/3213 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/31122 , H01L21/0332 , H01L21/3081 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3146 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A dry-etching method comprising the steps of forming carbon film on a substrate to be etched, forming a resist pattern on said carbon thin film, selectively etching said carbon film using said resist pattern as a mask by a plasma of a gas mixture of a gas containing fluorine atoms and a gas containing oxygen atoms which are mixed at an atomic ratio of fluorine to oxygen of 198:1 to 1:2 so as to form a carbon film pattern, and selectively etching said substrate to be etched using said carbon film pattern as a mask or said resist pattern and said carbon film pattern as masks.
摘要翻译：一种干蚀刻方法，包括以下步骤：在要蚀刻的基底上形成碳膜，在所述碳薄膜上形成抗蚀剂图案，使用所述抗蚀剂图案作为掩模，用等离子体选择性地蚀刻所述碳膜，含有氟原子的气体和以氟与氧的原子比混合为198:1〜1:2的含有氧原子的气体，以形成碳膜图案，并使用所述碳膜选择性地蚀刻所述蚀刻用基板图案作为掩模或所述抗蚀剂图案和所述碳膜图案作为掩模。

4. 发明授权

US5302240A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5302240A
公开(公告)日：1994-04-12
申请号：US20193
申请日：1993-02-19
申请人： Masaru Hori , Hiroyuki Yano , Keiji Horioka , Hisataka Hayashi , Sadayuki Jimbo , Haruo Okano , Kazuhiro Tomioka , Yasuhiro Ito , Haruki Mori
发明人： Masaru Hori , Hiroyuki Yano , Keiji Horioka , Hisataka Hayashi , Sadayuki Jimbo , Haruo Okano , Kazuhiro Tomioka , Yasuhiro Ito , Haruki Mori
IPC分类号： H01L21/033 , H01L21/308 , H01L21/311 , H01L21/314 , H01L21/3213 , H01L2/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/31122 , H01L21/0332 , H01L21/3081 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3146 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A dry-etching method comprising the steps of forming carbon film on a substrate to be etched, forming a resist pattern on said carbon thin film, selectively etching said carbon film using said resist pattern as a mask by a plasma of a gas mixture of a gas containing fluorine atoms and a gas containing oxygen atoms which are mixed at an atomic ratio of fluorine to oxygen of 198:1 to 1:2 so as to form a carbon film pattern, and selectively etching said substrate to be etched using said carbon film pattern as a mask or said resist pattern and said carbon film pattern as masks.
摘要翻译：一种干蚀刻方法，包括以下步骤：在要蚀刻的基底上形成碳膜，在所述碳薄膜上形成抗蚀剂图案，使用所述抗蚀剂图案作为掩模，用等离子体选择性地蚀刻所述碳膜，含有氟原子的气体和以氟与氧的原子比混合为198:1〜1:2的含有氧原子的气体，以形成碳膜图案，并使用所述碳膜选择性地蚀刻所述蚀刻用基板图案作为掩模或所述抗蚀剂图案和所述碳膜图案作为掩模。

5. 发明授权

US5240554A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5240554A
公开(公告)日：1993-08-31
申请号：US824095
申请日：1992-01-22
申请人： Masaru Hori , Hiroyuki Yano , Keiji Horioka , Hisataka Hayashi , Sadayuki Jimbo , Haruo Okano
发明人： Masaru Hori , Hiroyuki Yano , Keiji Horioka , Hisataka Hayashi , Sadayuki Jimbo , Haruo Okano
IPC分类号： H01L21/308 , H01L21/311 , H01L21/314 , H01L21/3213
CPC分类号： H01L21/31138 , H01L21/3081 , H01L21/31116 , H01L21/31144 , H01L21/3146 , H01L21/32136 , H01L21/32139 , Y10S438/945
摘要： A method of manufacturing a semiconductor device includes the steps of forming a carbon film on a target film formed on a substrate, forming an organic film pattern on the carbon film, etching the carbon film using the organic film pattern as a mask to form a carbon film pattern, and heating the substrate, supplying an etching gas having halogen atoms to a reaction area where the substrate is stored, applying an electric field to the reaction area to generate a discharge, and anisotropically etching the silicon oxide film using the carbon film pattern as a mask and a plasma formed by the discharge.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在形成在基片上的靶膜上形成碳膜，在碳膜上形成有机膜图案，使用有机膜图案作为掩模蚀刻碳膜，形成碳并对基板进行加热，将具有卤素原子的蚀刻气体供给到存储基板的反应区域，向反应区域施加电场以产生放电，并使用碳膜图案进行各向异性蚀刻氧化硅膜作为掩模和通过放电形成的等离子体。

6. 发明授权

US09583360B2 Substrate processing apparatus and substrate processing method 有权
标题翻译：基板加工装置及基板处理方法
公开(公告)号：US09583360B2
公开(公告)日：2017-02-28
申请号：US13424952
申请日：2012-03-20
申请人： Akio Ui , Hisataka Hayashi , Keisuke Kikutani
发明人： Akio Ui , Hisataka Hayashi , Keisuke Kikutani
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306 , H01L21/311 , H01J37/32
CPC分类号： H01L21/31116 , H01J37/32091 , H01J37/32146 , H01J37/32174
摘要： In one embodiment, a substrate processing apparatus, includes: a chamber; a first electrode disposed in the chamber; a second electrode disposed in the chamber to face the first electrode, and to hold a substrate; an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode; and a pulse power supply to repeatedly apply a voltage waveform including a negative voltage pulse and a positive voltage pulse of which delay time from the negative voltage pulse is 50 nano-seconds or less to the second electrode while superposing on the RF voltage.
摘要翻译：在一个实施例中，基板处理装置包括：腔室; 设置在所述室中的第一电极; 设置在所述腔室中以面对所述第一电极并且保持衬底的第二电极; RF电源，向第二电极施加频率为50MHz以上的RF电压; 以及脉冲电源，用于在叠加在RF电压上的同时，将包括负电压脉冲和负电压脉冲的延迟时间的正电压脉冲的电压波形重复地施加到第二电极50纳秒以下。

7. 发明授权

US08821744B2 Substrate processing method and substrate processing apparatus 有权
标题翻译：基板处理方法和基板处理装置
公开(公告)号：US08821744B2
公开(公告)日：2014-09-02
申请号：US13051771
申请日：2011-03-18
申请人： Akio Ui , Hisataka Hayashi
发明人： Akio Ui , Hisataka Hayashi
IPC分类号： B44C1/22
CPC分类号： H01L21/31116 , H01J37/32082 , H01J37/32146 , H01J37/32174
摘要： A substrate processing method using a substrate processing apparatus includes a first step and a second step. The first step is to apply a negative voltage pulse from a pulsed power supply to be included in the apparatus. The second step is to apply floating potential for an interval of time between the negative voltage pulse and a positive voltage pulse from the pulsed power supply subsequent to the negative voltage pulse. In addition, the apparatus includes a chamber, a first electrode, a second electrode, an RF power supply, and the pulsed power supply. The second electrode is provided so that the second electrode faces the first electrode to hold a substrate. The RF power supply applies an RF voltage having a frequency of 50 MHz or higher to the second electrode. The pulsed power supply repeatedly applies a voltage waveform with the RF voltage to the second electrode.
摘要翻译：使用基板处理装置的基板处理方法包括第一步骤和第二步骤。第一步是施加来自脉冲电源的负电压脉冲以包括在装置中。第二步是在负电压脉冲和负电压脉冲之后的脉冲电源的正电压脉冲之间的时间间隔上施加浮动电位。此外，该装置包括腔室，第一电极，第二电极，RF电源和脉冲电源。第二电极设置成使得第二电极面对第一电极以保持基板。 RF电源对第二电极施加频率为50MHz以上的RF电压。脉冲电源将具有RF电压的电压波形重复地施加到第二电极。

8. 发明授权

US08821684B2 Substrate plasma processing apparatus and plasma processing method 有权
标题翻译：基板等离子体处理装置和等离子体处理方法
公开(公告)号：US08821684B2
公开(公告)日：2014-09-02
申请号：US12363070
申请日：2009-01-30
申请人： Akio Ui , Naoki Tamaoki , Takashi Ichikawa , Hisataka Hayashi , Takeshi Kaminatsui , Shinji Himori , Norikazu Yamada , Takeshi Ohse , Jun Abe
发明人： Akio Ui , Naoki Tamaoki , Takashi Ichikawa , Hisataka Hayashi , Takeshi Kaminatsui , Shinji Himori , Norikazu Yamada , Takeshi Ohse , Jun Abe
IPC分类号： C23F1/00 , C23C16/50 , H01L21/306 , H01J37/32
CPC分类号： H01J37/32027 , H01J37/32045 , H01J37/32091
摘要： A substrate plasma processing apparatus includes a substrate holding electrode and a counter electrode which are arranged in a chamber, a high frequency generating device which applies a high frequency of 50 MHZ or higher to the substrate holding electrode, a DC negative pulse generating device which applies a DC negative pulse voltage in a manner of superimposing on the high frequency, and a controller controlling to cause intermittent application of the high frequency and cause intermittent application of the DC negative pulse voltage according to the timing of on or off of the high frequency.
摘要翻译：衬底等离子体处理装置包括布置在腔室中的衬底保持电极和对电极，向衬底保持电极施加50MHz以上的高频的高频发生装置，应用了DC负脉冲发生装置以高频重叠的方式设置直流负脉冲电压，以及控制器，根据高频开启或关闭的定时控制高频频率的间歇施加，直流负脉冲电压的间歇施加。

9. 发明申请

US20120080408A1 SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS 有权
标题翻译：基板加工方法和基板加工装置
公开(公告)号：US20120080408A1
公开(公告)日：2012-04-05
申请号：US13051771
申请日：2011-03-18
申请人： Akio UI , Hisataka Hayashi
发明人： Akio UI , Hisataka Hayashi
IPC分类号： H01L21/3065
CPC分类号： H01L21/31116 , H01J37/32082 , H01J37/32146 , H01J37/32174
摘要： A substrate processing method using a substrate processing apparatus includes a first step and a second step. The first step is to apply a negative voltage pulse from a pulsed power supply to be included in the apparatus. The second step is to apply floating potential for an interval of time between the negative voltage pulse and a positive voltage pulse from the pulsed power supply subsequent to the negative voltage pulse. In addition, the apparatus includes a chamber, a first electrode, a second electrode, an RF power supply, and the pulsed power supply. The second electrode is provided so that the second electrode faces the first electrode to hold a substrate. The RF power supply applies an RF voltage having a frequency of 50 MHz or higher to the second electrode. The pulsed power supply repeatedly applies a voltage waveform with the RF voltage to the second electrode.
摘要翻译：使用基板处理装置的基板处理方法包括第一步骤和第二步骤。第一步是施加来自脉冲电源的负电压脉冲以包括在装置中。第二步是在负电压脉冲与负电压脉冲之后的脉冲电源的负电压脉冲和正电压脉冲之间施加浮动电位。此外，该装置包括腔室，第一电极，第二电极，RF电源和脉冲电源。第二电极设置成使得第二电极面对第一电极以保持基板。 RF电源对第二电极施加频率为50MHz以上的RF电压。脉冲电源将具有RF电压的电压波形重复地施加到第二电极。

10. 发明授权

US5592024A Semiconductor device having a wiring layer with a barrier layer 失效
标题翻译：具有具有阻挡层的布线层的半导体器件
公开(公告)号：US5592024A
公开(公告)日：1997-01-07
申请号：US330998
申请日：1994-10-28
申请人： Hisako Aoyama , Kyoichi Suguro , Hiromi Niiyama , Hitoshi Tamura , Hisataka Hayashi , Tomonori Aoyama , Gaku Minamihaba , Tadashi Iijima
发明人： Hisako Aoyama , Kyoichi Suguro , Hiromi Niiyama , Hitoshi Tamura , Hisataka Hayashi , Tomonori Aoyama , Gaku Minamihaba , Tadashi Iijima
IPC分类号： H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/532 , H01L23/535 , H01L29/41 , H01L29/43
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76814 , H01L21/76822 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76847 , H01L21/76849 , H01L21/7685 , H01L21/76852 , H01L21/76856 , H01L21/76858 , H01L21/76867 , H01L21/76877 , H01L21/76885 , H01L21/76897 , H01L23/53233 , H01L23/53238 , H01L23/53242 , H01L23/53247 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2221/1036 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.
摘要翻译：半导体器件包括其中形成半导体元件的半导体衬底，形成在半导体衬底上的层间绝缘膜，通过等离子体氮化形成在层间绝缘膜上的绝缘阻挡层，用于防止构成布线层的金属的扩散形成在绝缘阻挡层上的用于防止金属扩散的导电阻挡层，以及由金属形成的布线层在导电阻挡层上。布线层的底部由导电阻挡层和绝缘阻挡层保护。因此，可以可靠地防止构成布线层的金属的扩散。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式