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1. 发明授权

US5942784A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5942784A
公开(公告)日：1999-08-24
申请号：US891558
申请日：1997-07-11
申请人： Takayuki Harima , Kenichi Nakamura , Mitsugi Ogura
发明人： Takayuki Harima , Kenichi Nakamura , Mitsugi Ogura
IPC分类号： H01L21/8238 , H01L27/08 , H01L27/092 , H03K19/094 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0921
摘要： A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.
摘要翻译：公开了一种实现高速访问并且防止由多个电源对闩锁进行任何功率输入序列的半导体器件。在芯片电压VDD较早输入的地方，N阱偏置电路9和P阱偏置电路10被激活，N型阱12和P型阱13分别被偏置。之后，虽然输入了接口电压VDDQ，但是不产生闭锁。另一方面，在接口电压VDDQ较早地输入端子8的情况下，N阱偏压电路9和P阱偏置电路10通过旁路电路15被激活，N型阱12和P- 类型井13有偏差。因此，尽管在此之后输入芯片电压VDD，但是不产生闩锁。

2. 发明授权

US4799193A Semiconductor memory devices 失效
标题翻译：半导体存储器件
公开(公告)号：US4799193A
公开(公告)日：1989-01-17
申请号：US917042
申请日：1986-10-09
申请人： Fumio Horiguchi , Yasuo Itoh , Mitsugi Ogura , Masaki Momodomi
发明人： Fumio Horiguchi , Yasuo Itoh , Mitsugi Ogura , Masaki Momodomi
IPC分类号： G11C11/404 , G11C11/407 , G11C11/4074 , G11C11/24
CPC分类号： G11C11/4074
摘要： A semiconductor memory device having at least one memory cell array block with a plurality of memory cells formed at the surface of a semiconductor substrate. Each memory cell includes a transistor and memory capacitor. The device further has a plurality of word lines for addressing the memory cells, a plurality of bit lines for reading from and writing to the memory capacitors, at least one cell plate formed on the semiconductor substrate, the cell plate forming a common electrode of the memory capacitors, a cell plate voltage generator for supplying a voltage of a level between the supply voltage and the ground voltage to the cell plate, and a control circuit for controlling the output impedance of the cell plate voltage generating unit.
摘要翻译：一种半导体存储器件，具有至少一个具有形成在半导体衬底的表面处的多个存储单元的存储单元阵列块。每个存储单元包括晶体管和存储电容器。该装置还具有用于寻址存储单元的多条字线，用于从存储电容器读取和写入存储电容器的多条位线，形成在半导体衬底上的至少一个单元板，形成公共电极的单元板存储电容器，用于向电池板提供电源电压和接地电压之间的电平的电池板电压发生器，以及用于控制电池板电压产生单元的输出阻抗的控制电路。

3. 发明授权

US4706249A Semiconductor memory device having error detection/correction function 失效
标题翻译：具有误差检测/校正功能的半导体存储器件
公开(公告)号：US4706249A
公开(公告)日：1987-11-10
申请号：US804177
申请日：1985-12-03
申请人： Kaoru Nakagawa , Mitsugi Ogura , Kenji Natori , Fujio Masuoka
发明人： Kaoru Nakagawa , Mitsugi Ogura , Kenji Natori , Fujio Masuoka
IPC分类号： G11C29/00 , G06F11/10 , G11C11/401 , G11C29/42
CPC分类号： G06F11/1008 , G06F11/1076 , G11C29/42
摘要： In the semiconductor memory device of the invention, a normal voltage detecting circuit and a high voltage detecting circuit are connected to a terminal for the purpose of receiving a write enable signal. When a signal of normal level is supplied to the terminal, the circuit controls data read or write with respect to a memory cell array in accordance with the level of the write enable signal. An error correction code circuit is rendered operative, and a soft error generated in data read from the memory cell array is corrected. When a high voltage is applied to the terminal, the circuit sets the memory device in the read mode. The circuit detects application of the high voltage to the terminal and supplies a predetermined signal to an ECC control circuit. In response to the signal, the ECC control circuit stops the operation of the ECC circuit. Data without any correction of soft errors is output from the memory device, and testing of hard errors is simplified.
摘要翻译：在本发明的半导体存储器件中，为了接收写入使能信号，正常电压检测电路和高电压检测电路连接到端子。当正常电平的信号被提供给终端时，电路根据写使能信号的电平来控制相对于存储单元阵列读或写的数据。使错误校正码电路工作，校正从存储单元阵列读出的数据中产生的软错误。当高电压施加到端子时，电路将存储器件设置在读取模式。电路检测到高电压对端子的施加，并向ECC控制电路提供预定的信号。响应该信号，ECC控制电路停止ECC电路的操作。从存储器件输出没有软错误校正的数据，简化了硬错误的测试。

4. 发明授权

US4611237A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4611237A
公开(公告)日：1986-09-09
申请号：US635474
申请日：1984-07-30
申请人： Kazunori Ohuchi , Mitsugi Ogura , Kenji Natori
发明人： Kazunori Ohuchi , Mitsugi Ogura , Kenji Natori
IPC分类号： H01L29/78 , H01L21/82 , H01L23/522 , H01L23/535 , H01L29/41 , H01L29/417
CPC分类号： H01L23/522 , H01L23/535 , H01L29/41725 , H01L2924/0002
摘要： A MOS transistor integrated circuit device has at least one interconnection layer crossing the source and drain regions of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer is formed on the surface of at least one of the source and drain regions of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes and electrically insulated from the interconnection layer.
摘要翻译： MOS晶体管集成电路器件具有与MOS晶体管的源区和漏极区交叉的至少一个互连层，使得它覆盖在这些源极和漏极区上。在MOS晶体管的源区和漏区中的至少一个的表面上形成导电层。导电层在其间具有绝缘层与互连层交叉，使得其位于互连层下面。导电层与源极和漏极引出电极分离并与互连层电绝缘。

5. 发明授权

US4992389A Making a self aligned semiconductor device 失效
标题翻译：制作自对准的半导体器件
公开(公告)号：US4992389A
公开(公告)日：1991-02-12
申请号：US142272
申请日：1988-01-04
申请人： Mitsugi Ogura , Shioji Ariizumi , Fumio Horiguchi , Fujio Masuoka
发明人： Mitsugi Ogura , Shioji Ariizumi , Fumio Horiguchi , Fujio Masuoka
IPC分类号： H01L29/94 , H01L21/336 , H01L21/768 , H01L27/112 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/76895 , H01L27/112 , H01L29/78 , H01L29/7835 , Y10S148/141
摘要： A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, and forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.
摘要翻译：一种使用自对准技术制造具有高集成密度和高可靠性的半导体器件的方法，包括在第一导电类型的半导体衬底上形成栅电极，并在其上方布置绝缘膜，形成一对第二导电类型的第一杂质区与衬底中的栅电极相互分离和自对准，并且在栅电极的至少一个侧面和上下绝缘膜上形成由绝缘体组成的壁，形成第二导电类型的第二高掺杂杂质区域在衬底中比第一杂质区域更深的相对于壁的自对准方式，形成连接到第二杂质区域的电极层，至少部分所述电极在所述栅电极的上绝缘膜上延伸，并且在所述电极层上选择性地形成布线层。

6. 发明授权

US4748596A Semiconductor memory device with sense amplifiers 失效
标题翻译：具有读出放大器的半导体存储器件
公开(公告)号：US4748596A
公开(公告)日：1988-05-31
申请号：US792197
申请日：1985-10-28
申请人： Mitsugi Ogura , Yasuo Itoh
发明人： Mitsugi Ogura , Yasuo Itoh
IPC分类号： G11C11/409 , G11C7/06 , G11C11/34 , G11C11/401 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4091
摘要： In a dynamic semiconductor memory, bit line pairs and word lines are perpendicular to each other and arranged in a matrix constituted by memory cells. Dummy cells are arranged at intersections between the bit line pairs and a pair of dummy cell word lines. The capacitance of each dummy cell is half that of the memory cell. A pre-sense amplifier and a main sense amplifier are arranged in each pair of bit lines. When data is read out from a selected memory cell, the pre-sense amplifiers are simultaneously activated to perform the pre-sensing operation. However, in the main sensing operation, only one specific main sense amplifier arranged in a certain bit line pair including the bit line connected to the selected memory cell is activated.
摘要翻译：在动态半导体存储器中，位线对和字线彼此垂直并且以由存储器单元构成的矩阵布置。虚拟单元被布置在位线对和一对虚拟单元字线之间的交点处。每个虚拟单元的电容是存储单元的一半。在每对位线中布置预读放大器和主读出放大器。当从所选择的存储单元读出数据时，预读放大器同时被激活以执行预感测操作。然而，在主感测操作中，仅激活布置在包括连接到所选择的存储器单元的位线的某一位线对中的一个特定主读出放大器。

7. 发明授权

US5227319A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5227319A
公开(公告)日：1993-07-13
申请号：US794660
申请日：1991-11-18
申请人： Mitsugi Ogura , Shioji Ariizumi , Fumio Horiguchi , Fujio Masuoka
发明人： Mitsugi Ogura , Shioji Ariizumi , Fumio Horiguchi , Fujio Masuoka
IPC分类号： H01L21/285 , H01L21/336 , H01L21/768 , H01L27/112 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28525 , H01L21/76895 , H01L27/112 , H01L29/78 , H01L29/7835 , Y10S148/131
摘要： A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.
摘要翻译：一种使用自对准技术制造具有高集成密度和高可靠性的半导体器件的方法，包括在第一导电类型的半导体衬底上形成栅电极，并在其上方布置绝缘膜，形成一对与衬底中的栅电极相互分离和自对准的第二导电类型的第一杂质区，在栅电极的至少一个侧面上形成由绝缘体构成的壁和上下绝缘膜，形成第二导电类型的第二高掺杂杂质区域相对于壁以自对准的方式在衬底中比第一杂质区域更深的深度，形成连接到第二杂质区域的电极层，至少部分电极，其延伸在栅电极的上绝缘膜上，并且在电极层上选择性地形成布线层。

8. 发明授权

US4798794A Method for manufacturing dynamic memory cell 失效
标题翻译：动态存储单元的制造方法
公开(公告)号：US4798794A
公开(公告)日：1989-01-17
申请号：US56726
申请日：1987-06-02
申请人： Mitsugi Ogura , Fujio Masuoka
发明人： Mitsugi Ogura , Fujio Masuoka
IPC分类号： H01L23/50 , H01L21/8242 , H01L27/108 , H01L29/96
CPC分类号： H01L27/10861 , H01L27/10829 , Y10S148/018
摘要： A first semiconductor layer of a P.sup.+ type is formed on a semiconductor substrate of a P.sup.- type and a mask layer is formed on a portion of the first semiconductor layer other than that area where a capacitor is to be formed. A hole is formed in a direction of a thickness of the first semiconductor layer, using the mask layer. An N.sup.+ is formed on the inner surface of the hole with the mask layer as a mask. An insulating film for capacitor formation is formed on the inner surface of the resultant hole and on that atea of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer acting as a capacitor electrode is formed on the capacitor formation insulating film. With the conductive layer as a mask, an impurity of an N type is doped into the first semiconductor layer to form a second semiconductor layer of a P.sup.- type in the surface portion of the first semiconductor layer. A MOS transistor is formed in the surface portion of the second conductive layer.

9. 发明授权

US4763178A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4763178A
公开(公告)日：1988-08-09
申请号：US928694
申请日：1986-11-07
申请人： Koji Sakui , Mitsugi Ogura
发明人： Koji Sakui , Mitsugi Ogura
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , Y10S257/911
摘要： A dynamic random access memory is disclosed which has memory cell units formed on a silicon substrate, each of which includes four memory cells, each of these including a MOS transistor and a MOS capacitor. One cell unit occupies a substantially square area of the surface of the substrate. The four memory cells included in this cell unit are arranged along the diagonal lines of the square area in the shape of a cross. The four transistors are connected to a common drain through a common drain region. The capacitors are respectively arranged at the four corners of the square area so as to have a relatively increased capacitor area, thereby obtaining a large capacitance.
摘要翻译：公开了一种动态随机存取存储器，其具有形成在硅衬底上的存储单元单元，每个存储单元包括四个存储单元，其中每一个包括MOS晶体管和MOS电容器。一个电池单元占据基板表面的基本上正方形的面积。包括在该单元单元中的四个存储单元沿着十字形形状的正方形区域的对角线布置。四个晶体管通过公共漏极区域连接到公共漏极。电容器分别布置在正方形区域的四个角处，以便具有相对增加的电容器面积，从而获得大的电容。

10. 发明授权

US4636981A Semiconductor memory device having a voltage push-up circuit 失效
标题翻译：具有电压上推电路的半导体存储器件
公开(公告)号：US4636981A
公开(公告)日：1987-01-13
申请号：US514107
申请日：1983-07-15
申请人： Mitsugi Ogura
发明人： Mitsugi Ogura
IPC分类号： G11C11/409 , G11C11/4094 , G11C11/40
CPC分类号： G11C11/4094
摘要： A semiconductor memory device includes charge storage type memory cells, word lines and a bit line connected to the memory cells, a sense amplifier for detecting the memory data on the bit line, and a voltage push-up circuit for setting up a potential on the bit line. The voltage push-up circuit at first sets the potential on the bit line at a power supply voltage level after the memory data having a high logic level is detected by the sense amplifier, and then pushes up the potential on the bit line to a higher potential level than the power supply voltage.
摘要翻译：半导体存储器件包括电荷存储型存储单元，字线和连接到存储单元的位线，用于检测位线上的存储器数据的读出放大器和用于在位线上建立电位的电压上推电路位线。电压上推电路首先在读出放大器检测到具有高逻辑电平的存储器数据之后，在电源电压电平下设置位线上的电位，然后将位线上的电位上升到更高电位高于电源电压。

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