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1. 发明授权

US4800530A Semiconductor memory system with dynamic random access memory cells 失效
标题翻译：具有动态随机存取存储单元的半导体存储器系统
公开(公告)号：US4800530A
公开(公告)日：1989-01-24
申请号：US85086
申请日：1987-08-13
申请人： Yasuo Itoh , Fumio Horiguchi , Shigeyoshi Watanabe , Kazunori Ohuchi , Mitsugi Ogura
发明人： Yasuo Itoh , Fumio Horiguchi , Shigeyoshi Watanabe , Kazunori Ohuchi , Mitsugi Ogura
IPC分类号： G11C11/40 , G11C7/00 , G11C7/10 , G11C7/22
CPC分类号： G11C7/22 , G11C7/00 , G11C7/1033
摘要： A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.
摘要翻译：动态随机存取存储器系统包括第一和第二存储体。连接到字线的多个存储单元被分组为第一组和第二组。第一组布置在第一存储体中，第二组布置在第二存储体中。提供读/写装置，其中从第一组的每个n位和从第二组的每个n位和第二组的每个n位被交替地读取和写入。每个位与列地址选通信号的切换同步读写。

2. 发明授权

US4799193A Semiconductor memory devices 失效
标题翻译：半导体存储器件
公开(公告)号：US4799193A
公开(公告)日：1989-01-17
申请号：US917042
申请日：1986-10-09
申请人： Fumio Horiguchi , Yasuo Itoh , Mitsugi Ogura , Masaki Momodomi
发明人： Fumio Horiguchi , Yasuo Itoh , Mitsugi Ogura , Masaki Momodomi
IPC分类号： G11C11/404 , G11C11/407 , G11C11/4074 , G11C11/24
CPC分类号： G11C11/4074
摘要： A semiconductor memory device having at least one memory cell array block with a plurality of memory cells formed at the surface of a semiconductor substrate. Each memory cell includes a transistor and memory capacitor. The device further has a plurality of word lines for addressing the memory cells, a plurality of bit lines for reading from and writing to the memory capacitors, at least one cell plate formed on the semiconductor substrate, the cell plate forming a common electrode of the memory capacitors, a cell plate voltage generator for supplying a voltage of a level between the supply voltage and the ground voltage to the cell plate, and a control circuit for controlling the output impedance of the cell plate voltage generating unit.
摘要翻译：一种半导体存储器件，具有至少一个具有形成在半导体衬底的表面处的多个存储单元的存储单元阵列块。每个存储单元包括晶体管和存储电容器。该装置还具有用于寻址存储单元的多条字线，用于从存储电容器读取和写入存储电容器的多条位线，形成在半导体衬底上的至少一个单元板，形成公共电极的单元板存储电容器，用于向电池板提供电源电压和接地电压之间的电平的电池板电压发生器，以及用于控制电池板电压产生单元的输出阻抗的控制电路。

3. 发明授权

US4748596A Semiconductor memory device with sense amplifiers 失效
标题翻译：具有读出放大器的半导体存储器件
公开(公告)号：US4748596A
公开(公告)日：1988-05-31
申请号：US792197
申请日：1985-10-28
申请人： Mitsugi Ogura , Yasuo Itoh
发明人： Mitsugi Ogura , Yasuo Itoh
IPC分类号： G11C11/409 , G11C7/06 , G11C11/34 , G11C11/401 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4091
摘要： In a dynamic semiconductor memory, bit line pairs and word lines are perpendicular to each other and arranged in a matrix constituted by memory cells. Dummy cells are arranged at intersections between the bit line pairs and a pair of dummy cell word lines. The capacitance of each dummy cell is half that of the memory cell. A pre-sense amplifier and a main sense amplifier are arranged in each pair of bit lines. When data is read out from a selected memory cell, the pre-sense amplifiers are simultaneously activated to perform the pre-sensing operation. However, in the main sensing operation, only one specific main sense amplifier arranged in a certain bit line pair including the bit line connected to the selected memory cell is activated.
摘要翻译：在动态半导体存储器中，位线对和字线彼此垂直并且以由存储器单元构成的矩阵布置。虚拟单元被布置在位线对和一对虚拟单元字线之间的交点处。每个虚拟单元的电容是存储单元的一半。在每对位线中布置预读放大器和主读出放大器。当从所选择的存储单元读出数据时，预读放大器同时被激活以执行预感测操作。然而，在主感测操作中，仅激活布置在包括连接到所选择的存储器单元的位线的某一位线对中的一个特定主读出放大器。

4. 发明授权

US07139201B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US07139201B2
公开(公告)日：2006-11-21
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

5. 发明授权

US06781895B1 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US06781895B1
公开(公告)日：2004-08-24
申请号：US09722474
申请日：2000-11-28
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C700
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

6. 发明授权

US06172911B2 Non-volatile semiconductor memory device with an improved verify voltage generator 失效
标题翻译：具有改进的验证电压发生器的非易失性半导体存储器件
公开(公告)号：US06172911B2
公开(公告)日：2001-01-09
申请号：US09283583
申请日：1999-04-01
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C1606
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

7. 发明授权

US5751634A Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor 失效
标题翻译：用于存储多值数据和其读出/写入方法的非易失性半导体存储器件
公开(公告)号：US5751634A
公开(公告)日：1998-05-12
申请号：US647629
申请日：1996-05-15
申请人： Yasuo Itoh
发明人： Yasuo Itoh
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/26 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C2211/5642 , G11C2211/5647
摘要： Memory cells each for storing 2-bit data are connected to a bit line. First and second flip-flop circuits are coupled to the bit line. The first flip-flop circuit holds the lower bit of 2-bit data read out from or written into the memory cell and the second flip-flop circuit holds the upper bit of 2-bit data read out from or written into the memory cell. At the data readout time, the upper bit is first read out from the memory cell and then the lower bit is read out from the memory cell. At the data writing time, the upper bit is first written into the memory cell and then the lower bit is written into the memory cell.
摘要翻译：每个用于存储2位数据的存储单元连接到位线。第一和第二触发器电路耦合到位线。第一触发器电路保持从存储单元读出或写入存储单元的2位数据的低位，并且第二触发器电路保持从存储单元读出或写入存储单元的2位数据的高位。在数据读出时，首先从存储单元读出高位，然后从存储单元读出低位。在数据写入时，首先将高位写入存储单元，然后将较低位写入存储单元。

8. 发明授权

US5557568A Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
标题翻译：具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5557568A
公开(公告)日：1996-09-17
申请号：US427265
申请日：1995-04-24
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，晶体管对位线进行充电。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。一种数据设定电路，用于在触发电路的第一和第二信号节点之一连接到预定电位，当位线在验证模式下处于充电电位时，从而将触发器电路设置在第二状态，而与在验证模式之前的状态。

9. 发明授权

US5368088A Apparatus of continuously casting a metal sheet 失效
标题翻译：连续铸造金属板的装置
公开(公告)号：US5368088A
公开(公告)日：1994-11-29
申请号：US42860
申请日：1993-04-05
申请人： Takashi Furuya , Hidemaro Takeuchi , Akio Kasama , Yasuo Itoh , Motoya Fujii , Hideki Oka , Shogo Matsumura , Kunimasa Sasaki , Keiichi Yamamoto
发明人： Takashi Furuya , Hidemaro Takeuchi , Akio Kasama , Yasuo Itoh , Motoya Fujii , Hideki Oka , Shogo Matsumura , Kunimasa Sasaki , Keiichi Yamamoto
IPC分类号： B22D11/06
CPC分类号： B22D11/0651 , B22D11/064 , B22D11/0697
摘要： Molten metal is supplied to a pouring basin formed between cooling members, such as movable cooling drums. A closed space is formed at a meniscus area whereat any one of the cooling members starts to come into contact with the molten metal, and a soluble gas or a mixture of soluble and insoluble gases is supplied to and filled in the closed space, thereby covering the meniscus area with the gas or the mixture. This arrangement enables a continuous casting of a thin metal sheet without surface cracks and having excellent surface characteristics.
摘要翻译：将熔融金属供应到形成在诸如可移动冷却鼓之类的冷却构件之间的倾倒盆中。在弯液面区域处形成封闭空间，其中任何一个冷却构件开始与熔融金属接触，并且将可溶性气体或可溶性和不溶性气体的混合物供给并填充在封闭空间中，从而覆盖弯液面与气体或混合物。这种布置使得能够连续铸造薄金属片而没有表面裂纹并且具有优异的表面特性。

10. 外观设计

USD305721S Electric finishing sander 失效
公开(公告)号：USD305721S
公开(公告)日：1990-01-30
申请号：US51062
申请日：1987-05-15
申请人： Fusao Fushiya , Yasuo Itoh
设计人： Fusao Fushiya , Yasuo Itoh

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