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1. 发明申请

US20050258860A1 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
公开(公告)号：US20050258860A1
公开(公告)日：2005-11-24
申请号：US11188980
申请日：2005-07-26
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： G06F1/32 , H03K19/00 , H03K19/003 , H04L25/02
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.

2. 发明授权

US06952112B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
标题翻译：输出缓冲电路，具有用于修改电源电压和晶体管尺寸的控制电路
公开(公告)号：US06952112B2
公开(公告)日：2005-10-04
申请号：US10416709
申请日：2000-11-30
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： G06F1/32 , H03K19/00 , H03K19/003 , H04L25/02
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.
摘要翻译：在本发明中，控制电路（111）控制电源电压（VDDQ）和外部输出缓冲器的晶体管尺寸，从而选择实现与传输线（100）的阻抗匹配的最低电源电压，从而通过电阻节省总线终端，从而实现了功耗的降低和数据传输的加速。数据传输期间的功耗与电源电压的平方成比例。如果外部输出缓冲器的工作电源电压降低，则功耗将相应降低。如果外部输出缓冲器的工作电源电压降低，其阻抗将明显增加; 并且同时，如果外部输出缓冲器的晶体管尺寸增加，则增加的阻抗将减小。通过使外部输出缓冲器的输出阻抗（导通电阻）与传输线的阻抗一致，可以在波形上输出信号而没有失真。

3. 发明授权

US06937059B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
公开(公告)号：US06937059B2
公开(公告)日：2005-08-30
申请号：US10667446
申请日：2003-09-23
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： G06F1/32 , H03K19/00 , H03K19/003 , H04L25/02
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.

4. 发明授权

US07123049B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
标题翻译：输出缓冲电路，具有用于修改电源电压和晶体管尺寸的控制电路
公开(公告)号：US07123049B2
公开(公告)日：2006-10-17
申请号：US11188980
申请日：2005-07-26
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： H03K19/003
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.
摘要翻译：在本发明中，控制电路（111）控制电源电压（VDDQ）和外部输出缓冲器的晶体管尺寸，从而选择实现与传输线（100）的阻抗匹配的最低电源电压，从而通过电阻节省总线终端，从而实现了功耗的降低和数据传输的加速。数据传输期间的功耗与电源电压的平方成比例。如果外部输出缓冲器的工作电源电压降低，则功耗将相应降低。如果外部输出缓冲器的工作电源电压降低，其阻抗将明显增加; 并且同时，如果外部输出缓冲器的晶体管尺寸增加，则增加的阻抗将减小。通过使外部输出缓冲器的输出阻抗（导通电阻）与传输线的阻抗一致，可以在波形上输出信号而没有失真。

5. 发明申请

US20180348169A1 System and Method for Assessment of Irregularity in a Wooden Material Surrounded by a Substrate 审中-公开
公开(公告)号：US20180348169A1
公开(公告)日：2018-12-06
申请号：US15773032
申请日：2016-11-04
申请人： Peter Lee , Wayne Hall
发明人： Peter Lee , Wayne Hall
IPC分类号： G01N29/11 , G01N29/04 , G01N29/06 , G01N29/26 , G01N29/28 , G01N29/48
CPC分类号： G01N29/11 , G01N29/043 , G01N29/0645 , G01N29/0672 , G01N29/069 , G01N29/07 , G01N29/26 , G01N29/262 , G01N29/28 , G01N29/48 , G01N33/46 , G01N2291/0238 , G01N2291/102 , G01N2291/106
摘要： A system for assessment of irregularity in wooden material below the surface of a substrate, from above the surface of the substrate. The wooden material extending from below to above the surface of the substrate and surrounded by the substrate below the surface of the substrate. The system comprising at least one transmitter and receiver or transducer arranged to transmit energy through the material from above the surface of the substrate towards the part of the material below the surface, and to receive energy reflected from the material back through the surface, and a processor arranged to analyse the reflected energy and provide an indication of irregularity in the material below the surface of the substrate.

6. 发明授权

US08999786B1 Reducing source contact to gate spacing to decrease transistor pitch 有权
标题翻译：将源触点减小到栅极间距，以减小晶体管间距
公开(公告)号：US08999786B1
公开(公告)日：2015-04-07
申请号：US12052573
申请日：2008-03-20
申请人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/336 , H01L29/788 , H01L21/027
CPC分类号： H01L29/41775 , H01L21/027 , H01L21/823425 , H01L27/11568 , H01L29/0847 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7835 , H01L29/792
摘要： Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.
摘要翻译：公开了具有减小的半导体器件中与栅极间隔的源极接触的晶体管的方法和结构。在一个实施例中，形成晶体管的方法可以包括：在晶体管的有源区上形成栅极; 形成与有源区域中的栅极对准的源区和漏区; 在源极和漏极区域上形成源极和漏极接触，其中晶体管的栅极至源极接触的间隔小于晶体管的栅极至漏极接触的间隔; 并且使用一个或多个修改的掩模来形成源极区和漏极区的掺杂分布。

7. 发明授权

US08478722B2 Enterprise level business information networking for changes in a database 有权
标题翻译：企业级业务信息网络，用于更改数据库
公开(公告)号：US08478722B2
公开(公告)日：2013-07-02
申请号：US12945410
申请日：2010-11-12
申请人： Peter Lee , Vinod Mehra , Rob Woollen
发明人： Peter Lee , Vinod Mehra , Rob Woollen
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F17/30339 , G06F17/30082 , G06F17/30165 , G06F17/30221 , G06F17/3023 , G06F17/30424 , G06F21/6227 , G06Q10/10 , G06Q30/02 , G06Q50/01
摘要： Systems, apparatus, and methods for implementing enterprise level social and business information networking are provided. Users can receive relevant information about a database system and its users at an appropriate time. Users can then use this relevant information to reduce errors and limit redundant efforts. For example, an update of a record in the database can be identified, and a story created automatically about the update and sent to the users that are following the record. Which updates have stories created and which stories are to be sent to which users can be configured. Other events besides updating of records can also be tracked. For example, actions of a user that result in an event can be tracked, where such tracking can also be configurable. Subscriptions to follow an object can be automatic, and access checks can be used to ensure that unauthorized users do not see certain data.
摘要翻译：提供了实施企业级社会和商业信息网络的系统，设备和方法。用户可以在适当的时间接收有关数据库系统及其用户的相关信息。然后，用户可以使用此相关信息来减少错误并限制冗余工作。例如，可以识别数据库中记录的更新，并自动创建关于更新的故事，并将其发送给跟随记录的用户。哪些更新创建了故事，哪些故事要发送给哪些用户可以配置。还可以跟踪除记录更新之外的其他事件。例如，可以跟踪导致事件的用户的动作，这样的跟踪也可以被配置。可以自动跟踪对象的订阅，并且可以使用访问检查来确保未经授权的用户看不到某些数据。

8. 发明授权

US08285524B2 Simulation method for transistor unsuitable for existing model 有权
标题翻译：晶体管的仿真方法不适合现有的模型
公开(公告)号：US08285524B2
公开(公告)日：2012-10-09
申请号：US12608551
申请日：2009-10-29
申请人： Yasuhiro Namba , Peter Lee
发明人： Yasuhiro Namba , Peter Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.
摘要翻译：模拟方法包括基于其中写入晶体管的寿命数据或晶体管的劣化速率的数据的表来确定应力时间和漏极电流的劣化率之间的关系，并计算变化量在根据劣化率的漏极电流中，使用其中写入表示依赖于电压的漏极电流的变化的信息的表，基于在劣化后晶体管的漏极电流的实际测量数据，初始的漏极电流特定晶体管模型的状态，以及应力时间与漏极电流的劣化率之间的关系。

9. 发明授权

US07888166B2 Method to form high efficiency GST cell using a double heater cut 有权
标题翻译：使用双加热器切割形成高效GST电池的方法
公开(公告)号：US07888166B2
公开(公告)日：2011-02-15
申请号：US12724266
申请日：2010-03-15
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L21/00 , H01L29/18
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。还描述了其它实施例。

10. 发明授权

US07801894B1 Method and apparatus for harvesting file system metadata 有权
标题翻译：用于收集文件系统元数据的方法和装置
公开(公告)号：US07801894B1
公开(公告)日：2010-09-21
申请号：US11262283
申请日：2005-10-28
申请人： Jeff G. Bone , Laura Arbilla , Keith Zoellner , Bradley Might , Peter Lee
发明人： Jeff G. Bone , Laura Arbilla , Keith Zoellner , Bradley Might , Peter Lee
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30091
摘要： A harvester is disclosed for harvesting metadata of managed objects (files and directories) across file systems which are generally not interoperable in an enterprise environment. Harvested metadata may include 1) file system attributes such as size, owner, recency; 2) content-specific attributes such as the presence or absence of various keywords (or combinations of keywords) within documents as well as concepts comprised of natural language entities; 3) synthetic attributes such as mathematical checksums or hashes of file contents; and 4) high-level semantic attributes that serve to classify and categorize files and documents. The classification itself can trigger an action in compliance with a policy rule. Harvested metadata are stored in a metadata repository to facilitate the automated or semi-automated application of policies.
摘要翻译：披露收割机用于在企业环境中通常不能互操作的文件系统上收集托管对象（文件和目录）的元数据。收获的元数据可能包括1）文件系统属性，如大小，所有者，新近度; 2）内容特定的属性，例如文档中各种关键字（或关键字的组合）的存在或不存在以及由自然语言实体组成的概念; 3）合成属性，如数学校验和或文件内容的散列; 和4）用于对文件和文档进行分类和分类的高级语义属性。分类本身可以触发符合策略规则的操作。收获的元数据存储在元数据存储库中，以便于自动或半自动应用策略。

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