专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07939445B1 High density via and metal interconnect structures, and methods of forming the same 有权
标题翻译：高密度通孔和金属互连结构及其形成方法
公开(公告)号：US07939445B1
公开(公告)日：2011-05-10
申请号：US12049229
申请日：2008-03-14
申请人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838
摘要： Methods and structures for interconnects in semiconductor devices are described. A method of forming a mask pattern for a metal layer in an interconnect can include searching a layout for a metal feature with a predetermined size and an interconnect layer aligned thereto, removing the metal feature from the layout to form a modified layout, and reforming the mask pattern using the modified layout. The metal interconnect may include a first pattern of metal lines, each having a minimum feature size in a layout view in no more than one dimension; a dielectric layer on or over the first pattern of metal lines, having a substantially planar horizontal upper surface; and vias or contacts in the dielectric layer, the vias or contacts contacting a top surface of the first pattern of metal lines and a top surface of silicon structures, vias, or contacts below the first pattern of metal lines.
摘要翻译：描述了半导体器件中互连的方法和结构。在互连中形成用于金属层的掩模图案的方法可以包括搜索具有预定尺寸的金属特征的布局和与其对准的互连层，从布局去除金属特征以形成修改的布局，并且重新形成掩模图案使用修改的布局。金属互连可以包括金属线的第一图案，每个金属线在布局视图中具有不超过一个维度的最小特征尺寸; 金属线的第一图案上或之上的介电层，具有基本上平面的水平上表面; 以及电介质层中的通孔或触点，接触金属线的第一图案的顶表面的通孔或触点以及金属线的第一图案之下的硅结构，通孔或触点的顶表面。

2. 发明授权

US07994052B1 High-density patterning 有权
标题翻译：高密度图案化
公开(公告)号：US07994052B1
公开(公告)日：2011-08-09
申请号：US12045528
申请日：2008-03-10
申请人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/44
CPC分类号： H01L21/76816
摘要： Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.
摘要翻译：本文描述了用于图案化高密度特征的方法。本发明的实施例提供了一种方法，包括对图案的第一子集进行图案化，所述第一子集被配置成在所述衬底上形成多个线，以及图案化所述图案的第二子集，所述第二子集被配置为形成多个岛其中所述图案化所述第一子集并且所述图案化所述第二子集包括至少两个单独的图案化操作。

3. 发明授权

US07985616B1 Methods to form wide heater trenches and to form memory cells to engage heaters 有权
标题翻译：形成宽加热器沟槽并形成记忆单元以接合加热器的方法
公开(公告)号：US07985616B1
公开(公告)日：2011-07-26
申请号：US12060810
申请日：2008-04-01
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L21/00
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： Embodiments of the present invention provide a method that includes providing a wafer including multiple cells, each cell including at least one emitter, and performing a lithographic operation on the wafer. The lithographic operation comprises forming heater trenches adjacent the emitters, each heater trench having a width that extends over at least respective portions of two cells. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极，并在晶片上执行光刻操作。光刻操作包括在发射器附近形成加热器沟槽，每个加热器沟槽具有在两个单元的至少相应部分上延伸的宽度。还描述了其它实施例。

4. 发明授权

US07892936B1 Self aligned integration of high density phase change memory with thin film access device 有权
标题翻译：高密度相变存储器与薄膜存取器件的自对准集成
公开(公告)号：US07892936B1
公开(公告)日：2011-02-22
申请号：US12435713
申请日：2009-05-05
申请人： Albert Wu , Runzi Chang
发明人： Albert Wu , Runzi Chang
IPC分类号： H01L21/8239 , H01L45/00
CPC分类号： H01L27/2463 , H01L27/2418 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Embodiments of the present invention provide a method that includes depositing a first electrode film on one or more wordline structures, depositing a phase change material (PCM) film on the first electrode film, depositing a second electrode film on the PCM film, depositing a third electrode film on the second electrode film, depositing an access device film on the third electrode film, and depositing a fourth electrode film on the access device film to form a stack of films, wherein the stack of films comprises the first electrode film, the PCM film, the second electrode film, the third electrode film, the access device film, and the fourth electrode film. Other embodiments may be described and/or claimed.
摘要翻译：本发明的实施例提供了一种方法，其包括在一个或多个字线结构上沉积第一电极膜，在第一电极膜上沉积相变材料（PCM）膜，在PCM膜上沉积第二电极膜，在所述第二电极膜上形成电极膜，在所述第三电极膜上沉积存取器件膜，以及在所述存取器件膜上沉积第四电极膜以形成一叠膜，其中所述膜堆包括所述第一电极膜，所述PCM 膜，第二电极膜，第三电极膜，存取装置膜和第四电极膜。可以描述和/或要求保护其他实施例。

5. 发明授权

US07807539B1 Ion implantation and process sequence to form smaller base pick-up 有权
标题翻译：离子注入和工艺顺序形成较小的基座
公开(公告)号：US07807539B1
公开(公告)日：2010-10-05
申请号：US12056052
申请日：2008-03-26
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L21/8222 , H01L21/331
CPC分类号： H01L29/0804 , H01L29/66272
摘要： Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.
摘要翻译：本文描述了用于形成双极结型晶体管器件的方法。用于形成双极结型晶体管器件的方法可以包括用第一掺杂剂掺杂衬底的第一部分以形成基极拾取区域，并且在掺杂衬底的第一部分之后，将衬底的第二部分用第二掺杂剂以形成至少一个发射极区域。双极结型晶体管器件可以包括浮动集电极，在这种情况下，双极结型晶体管器件可以作为二极管来工作，以改善发射极电流。

6. 发明授权

US09275985B1 RC networks that include an integrated high resistance resistor on top of a MOS capacitor 有权
标题翻译： RC网络在MOS电容器的顶部包括一个集成的高电阻电阻
公开(公告)号：US09275985B1
公开(公告)日：2016-03-01
申请号：US13538867
申请日：2012-06-29
申请人： Chuan-Cheng Cheng , Runzi Chang , Bo Wang
发明人： Chuan-Cheng Cheng , Runzi Chang , Bo Wang
IPC分类号： H01L27/06 , H01L27/11
CPC分类号： H01L27/0629 , H01L27/1112
摘要： An apparatus including a resistor capacitor network that includes an integrated high resistance resistor on top of a MOS capacitor. The resistor capacitor network includes a metal oxide semiconductor capacitor portion that includes a high-k gate oxide layer. The value of k is in a range of 4.0 to 100.0. The resistor capacitor network further includes a high resistance polysilicon gate layer formed over the high-k gate oxide layer. The resistance of the polysilicon gate layer is in a range of 100 to 2000 ohms per square.
摘要翻译：一种包括电阻电容器网络的装置，其包括在MOS电容器顶部的集成的高电阻电阻器。电阻电容器网络包括包含高k栅极氧化物层的金属氧化物半导体电容器部分。 k的值在4.0〜100.0的范围内。电阻电容器网络还包括形成在高k栅极氧化物层上的高电阻多晶硅栅极层。多晶硅栅极层的电阻在100-2000欧姆/平方的范围内。

7. 发明授权

US08999786B1 Reducing source contact to gate spacing to decrease transistor pitch 有权
标题翻译：将源触点减小到栅极间距，以减小晶体管间距
公开(公告)号：US08999786B1
公开(公告)日：2015-04-07
申请号：US12052573
申请日：2008-03-20
申请人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/336 , H01L29/788 , H01L21/027
CPC分类号： H01L29/41775 , H01L21/027 , H01L21/823425 , H01L27/11568 , H01L29/0847 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7835 , H01L29/792
摘要： Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.
摘要翻译：公开了具有减小的半导体器件中与栅极间隔的源极接触的晶体管的方法和结构。在一个实施例中，形成晶体管的方法可以包括：在晶体管的有源区上形成栅极; 形成与有源区域中的栅极对准的源区和漏区; 在源极和漏极区域上形成源极和漏极接触，其中晶体管的栅极至源极接触的间隔小于晶体管的栅极至漏极接触的间隔; 并且使用一个或多个修改的掩模来形成源极区和漏极区的掺杂分布。

8. 发明申请

US20110186998A1 RECESSED SEMICONDUCTOR SUBSTRATES 有权
标题翻译：残留的半导体衬底
公开(公告)号：US20110186998A1
公开(公告)日：2011-08-04
申请号：US13012644
申请日：2011-01-24
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域，以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔以及耦合到半导体衬底的管芯，该管芯电耦合到形成在半导体衬底的凹陷区域中的一个或多个通孔。可以描述和/或要求保护其他实施例。

9. 发明授权

US07888166B2 Method to form high efficiency GST cell using a double heater cut 有权
标题翻译：使用双加热器切割形成高效GST电池的方法
公开(公告)号：US07888166B2
公开(公告)日：2011-02-15
申请号：US12724266
申请日：2010-03-15
申请人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Runzi Chang , Chien-Chuan Wei , Winston Lee , Peter Lee
IPC分类号： H01L21/00 , H01L29/18
CPC分类号： H01L27/2463 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。还描述了其它实施例。

10. 发明授权

US07745809B1 Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips 有权
标题翻译：具有改进的发射体触点，改善的GST电池可靠性的超高密度相变存储器以及使用柱式微通道条带的高度匹配的UHD GST电池
公开(公告)号：US07745809B1
公开(公告)日：2010-06-29
申请号：US12062444
申请日：2008-04-03
申请人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
发明人： Pantas Sutardja , Albert Wu , Chien-Chuan Wei , Runzi Chang , Winston Lee , Peter Lee
IPC分类号： H01L29/04
CPC分类号： H01L45/1233 , H01L27/0688 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Embodiments of the present invention provide an apparatus comprising a substrate comprising an emitter layer and at least one emitter interface adjacent to the emitter layer, and a metal protective layer on a top surface of the at least one emitter interface. A method of manufacturing such an apparatus is also disclosed. The method may include performing plasma nitridation directed at column micro-trench strips. Other embodiments are also described.
摘要翻译：本发明的实施例提供了一种装置，其包括：衬底，其包括发射极层和与发射极层相邻的至少一个发射极接口，以及在所述至少一个发射极接口的顶表面上的金属保护层。还公开了制造这种装置的方法。该方法可以包括执行针对柱状微沟槽条带的等离子体氮化。还描述了其它实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式