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1. 发明授权

US06937059B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
公开(公告)号：US06937059B2
公开(公告)日：2005-08-30
申请号：US10667446
申请日：2003-09-23
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： G06F1/32 , H03K19/00 , H03K19/003 , H04L25/02
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.

2. 发明申请

US20050258860A1 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
公开(公告)号：US20050258860A1
公开(公告)日：2005-11-24
申请号：US11188980
申请日：2005-07-26
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： G06F1/32 , H03K19/00 , H03K19/003 , H04L25/02
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.

3. 发明授权

US06952112B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
标题翻译：输出缓冲电路，具有用于修改电源电压和晶体管尺寸的控制电路
公开(公告)号：US06952112B2
公开(公告)日：2005-10-04
申请号：US10416709
申请日：2000-11-30
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： G06F1/32 , H03K19/00 , H03K19/003 , H04L25/02
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.
摘要翻译：在本发明中，控制电路（111）控制电源电压（VDDQ）和外部输出缓冲器的晶体管尺寸，从而选择实现与传输线（100）的阻抗匹配的最低电源电压，从而通过电阻节省总线终端，从而实现了功耗的降低和数据传输的加速。数据传输期间的功耗与电源电压的平方成比例。如果外部输出缓冲器的工作电源电压降低，则功耗将相应降低。如果外部输出缓冲器的工作电源电压降低，其阻抗将明显增加; 并且同时，如果外部输出缓冲器的晶体管尺寸增加，则增加的阻抗将减小。通过使外部输出缓冲器的输出阻抗（导通电阻）与传输线的阻抗一致，可以在波形上输出信号而没有失真。

4. 发明授权

US07123049B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
标题翻译：输出缓冲电路，具有用于修改电源电压和晶体管尺寸的控制电路
公开(公告)号：US07123049B2
公开(公告)日：2006-10-17
申请号：US11188980
申请日：2005-07-26
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： H03K19/003
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.
摘要翻译：在本发明中，控制电路（111）控制电源电压（VDDQ）和外部输出缓冲器的晶体管尺寸，从而选择实现与传输线（100）的阻抗匹配的最低电源电压，从而通过电阻节省总线终端，从而实现了功耗的降低和数据传输的加速。数据传输期间的功耗与电源电压的平方成比例。如果外部输出缓冲器的工作电源电压降低，则功耗将相应降低。如果外部输出缓冲器的工作电源电压降低，其阻抗将明显增加; 并且同时，如果外部输出缓冲器的晶体管尺寸增加，则增加的阻抗将减小。通过使外部输出缓冲器的输出阻抗（导通电阻）与传输线的阻抗一致，可以在波形上输出信号而没有失真。

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