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1. 发明授权

US06507527B1 Memory line discharge before sensing 有权
标题翻译：感应前存储线放电
公开(公告)号：US06507527B1
公开(公告)日：2003-01-14
申请号：US09698614
申请日：2000-10-27
申请人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
发明人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/12
摘要： A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.
摘要翻译：一种通过将数据线从高于期望电压电平的电压电平放电到大约期望的电压电平，在数据线在低功率存储器件中被感测之前将数据线充电到期望的电压电平的方法。通过使用N型晶体管将数据线放电至期望的电压电平，可以用更便宜的组件更快地达到电压电平。

2. 发明授权

US06347052B1 Word line decoding architecture in a flash memory 有权
标题翻译：字线解码架构在闪存中
公开(公告)号：US06347052B1
公开(公告)日：2002-02-12
申请号：US09690554
申请日：2000-10-17
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C8/10
摘要： A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.
摘要翻译：描述了具有字线解码和选择架构的闪速存储器。闪速存储器包括存储单元的第一和第二扇区，第一和第二本地驱动电路，第一，第二和第三解码电路以及驱动电路。第一存储器单元的第一扇区包括耦合到第一存储器单元的第一多个字线，每个字线能够是第一选定的字线。第二存储器单元的第二扇区包括类似的局部驱动器电路独立地耦合到第一扇区的第一和第二多个字线的每个字线。每个解码电路包括解码电路的第一和第二侧。解码电路的第一侧激活第一选定的多个本地驱动器电路，并且解码电路的第二侧激活第二选定的多个局部驱动器电路。第二解码电路耦合到第一本地驱动电路，并将第一升压电压提供给耦合到第一本地驱动电路的第一选定字线。第三解码电路耦合到第二本地驱动电路，并将第二升压电压提供给第二选定字线。驱动电路向第一解码电路，第二解码电路，第三解码电路，第一本地驱动电路和第二本地驱动电路提供一系列升压电压。

3. 发明授权

US06229735B1 Burst read mode word line boosting 有权
标题翻译：突发读取模式字线提升
公开(公告)号：US06229735B1
公开(公告)日：2001-05-08
申请号：US09638055
申请日：2000-08-11
申请人： Takao Akaogi , Kendra Nguyen , Yong Kim , Lee Cleveland
发明人： Takao Akaogi , Kendra Nguyen , Yong Kim , Lee Cleveland
IPC分类号： G11C1606
CPC分类号： G11C8/18 , G11C8/08
摘要： A burst read mode operation is provided that boosts the voltage of a word line while the bit lines of the row are selected for reading. When the column group address bits read the last column group of cells in the row, a pulse signal is generated which temporarily reduces the boosted voltage to allow the X-decoder to select the next word line. An alternative delay element is also provided which generates an ATD pulse with a longer duration when the column group address bits are at the end of a row and a shorter duration pulse at other times.
摘要翻译：提供突发读取模式操作，其提高字线的电压，同时选择行的位线用于读取。当列组地址位读取行中的最后一列单元格时，产生脉冲信号，临时降低升压电压，以允许X解码器选择下一个字线。还提供了另一种延迟元件，当列组地址位在行的末尾，而在其他时间具有较短的持续时间脉冲时，其产生具有较长持续时间的ATD脉冲。

4. 发明授权

US06351420B1 Voltage boost level clamping circuit for a flash memory 有权
标题翻译：用于闪存的电压升压电平钳位电路
公开(公告)号：US06351420B1
公开(公告)日：2002-02-26
申请号：US09595519
申请日：2000-06-16
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/12 , G11C16/30
摘要： A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.
摘要翻译：用于闪存（100）的升压电路（111）包括升压电路（110），其能够将闪存的电源电压（VCC）的一部分升压到足以访问的字线电压电平存储器的核心单元阵列（102）中的核心单元。升压电路还包括用于向升压电路提供非零调节电压（VCL）的平衡或钳位电路（112），以在电源电压超过时减小升压电路可用于升压的电源电压部分一定的价值。

5. 发明授权

US06243316B1 Voltage boost reset circuit for a flash memory 有权
标题翻译：闪存的升压复位电路
公开(公告)号：US06243316B1
公开(公告)日：2001-06-05
申请号：US09501159
申请日：2000-02-09
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/08
摘要： A voltage boost circuit (111) for a memory (100) includes a boosting circuit (110) which is coupled to a boosted node (120) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (112) coupled to the boosted node and including a switchable zero-threshold transistor (202) for resetting the boosted node to a reset voltage (VCC).
摘要翻译：用于存储器（100）的升压电路（111）包括升压电路（110），其被耦合到升压节点（120）以升高用于访问存储器的核心单元的字线电压。升压电路还包括耦合到升压节点的复位电路（112），并且包括用于将升压节点复位到复位电压（VCC）的可切换零阈值晶体管（202）。

6. 发明授权

US06377488B1 Fast-erase memory devices and method for reducing erasing time in a memory device 有权
标题翻译：快速擦除存储器件和减少存储器件中擦除时间的方法
公开(公告)号：US06377488B1
公开(公告)日：2002-04-23
申请号：US09645623
申请日：2000-08-24
申请人： Yong Kim , Kendra Nguyen
发明人： Yong Kim , Kendra Nguyen
IPC分类号： G11C1606
CPC分类号： G11C16/3472 , G11C16/16 , G11C16/344 , G11C16/3468
摘要： A non-volatile semiconductor memory device comprising a memory array, the memory array divided into a plurality of sectors, each sector comprising a plurality of memory cells, which can be electrically erased, and an erase-verify circuit, capable of simultaneously erasing multiple memory sectors. The erase-verify circuit simultaneously erases a plurality memory sectors, and verifies that the memory cells in a selected memory sector of the plurality of memory sectors is erased. When it determines that the selected memory sector is not erased, it again erases the plurality of memory sectors and again verifies whether the selected memory sector is erased. The erasing of the plurality of memory sectors is repeated until it is verified that the memory cells in the selected memory sector is erased.
摘要翻译：一种非易失性半导体存储器件，包括存储器阵列，被划分成多个扇区的存储器阵列，每个扇区包括可被电擦除的多个存储单元，以及擦除验证电路，能够同时擦除多个存储器部门。擦除验证电路同时擦除多个存储器扇区，并且验证多个存储器扇区中所选择的存储器扇区中的存储单元被擦除。当确定所选择的存储器扇区未被擦除时，它再次擦除多个存储器扇区，并且再次验证所选择的存储器扇区是否被擦除。重复擦除多个存储器扇区，直到验证所选存储器扇区中的存储单元被擦除为止。

7. 发明授权

US06567289B1 Physical memory layout with various sized memory sectors 有权
标题翻译：物理内存布局与各种大小的内存扇区
公开(公告)号：US06567289B1
公开(公告)日：2003-05-20
申请号：US09644359
申请日：2000-08-23
申请人： Lee Cleveland , Yong Kim
发明人： Lee Cleveland , Yong Kim
IPC分类号： G11C506
CPC分类号： G11C5/025
摘要： The physical layout of a semiconductor memory device having memory sectors of varying sizes can be arranged such that the larger and smaller memory sectors are addressed by x-decoders and y-decoders via word lines and bit lines, respectively. The smaller memory sectors are laid out such that some of the small memory sectors are connected with a y-decoder or multiple y-decoders via different bit-lines. The smaller memory sectors are interspersed with the large memory sectors and an area near a corner of the memory device that can be used for other components such as peripheral devices. Optional physical to logical mapping of address allow the smaller memory sectors to be addressed in the first or the last memory addresses.
摘要翻译：可以布置具有不同大小的存储器扇区的半导体存储器件的物理布局，使得较大和较小的存储器扇区分别经由字线和位线被x解码器和y解码器寻址。布置较小的存储器扇区，使得一些小存储器扇区通过不同的位线与y解码器或多个y解码器连接。更小的存储器扇区散布有大的存储器扇区和靠近存储器件的角落的区域，其可以用于诸如外围设备的其他组件。地址的可选物理到逻辑映射允许在第一个或最后一个存储器地址中寻址更小的存储器扇区。

8. 发明申请

US20070155033A1 Method of manufacturing light emitting diode package 审中-公开
标题翻译：制造发光二极管封装的方法
公开(公告)号：US20070155033A1
公开(公告)日：2007-07-05
申请号：US11649914
申请日：2007-01-05
申请人： Yong Kim , Seog Choi , Yong Kim , Sang Shin
发明人： Yong Kim , Seog Choi , Yong Kim , Sang Shin
IPC分类号： H01L21/00
CPC分类号： B29C41/12 , B29C41/20 , B29C41/36 , B29C41/50 , B29L2011/00 , H01L33/52 , H01L2224/48091 , H01L2924/00014
摘要： A method of manufacturing an LED package. The method includes dispensing a transparent resilient resin on an LED package body and overturning an entire structure to form an LED lens integrally provided to the LED package body. This prevents extra processes and costs incurring from forming intermediate layers and obviates degradation in reliability and light extraction efficiency due to additional interfaces.
摘要翻译：一种制造LED封装的方法。该方法包括将透明弹性树脂分配在LED封装主体上并翻转整个结构以形成一体地提供到LED封装体的LED透镜。这防止了由于附加界面而形成中间层而导致额外的工艺和成本，并且消除了可靠性和光提取效率的降低。

9. 发明申请

US20060121815A1 Method of manufacturing barrier ribs for pdp by capillary molding of paste and paste compositions therefor 失效
标题翻译：通过毛细管成型用于制造pdp隔壁的糊剂和糊剂组合物的方法
公开(公告)号：US20060121815A1
公开(公告)日：2006-06-08
申请号：US10521196
申请日：2003-07-15
申请人： Yong Kim , Yong Kim , Sung Cho
发明人： Yong Kim , Yong Kim , Sung Cho
IPC分类号： H01J9/24
CPC分类号： H01J9/242 , H01J11/12 , H01J11/36
摘要： Disclosed is a method of manufacturing rear plate barrier ribs for Plasma Display Panel (PDP), which includes the steps of: forming barrier ribs by infiltrating the barrier rib forming paste into grooves of a mold by using the capillary phenomenon, and then sintering the paste. This method causes rare environmental pollution, enables to make barrier ribs having fine and complex shapes and reduces material costs required for the barrier rib. Thus, the method may improve quality of PDP and reduce manufacture costs of the rear plate.
摘要翻译：公开了一种制造等离子体显示面板（PDP）的后板阻挡肋的方法，其包括以下步骤：通过使用毛细管现象将隔壁形成膏渗透到模具的凹槽中，然后烧结浆料。这种方法造成罕见的环境污染，能够形成具有精细和复杂形状的隔肋，并且减少隔壁所需的材料成本。因此，该方法可以提高PDP的质量并降低后板的制造成本。

10. 发明申请

US20070063214A1 Light emitting diode package and method for manufacturing the same 审中-公开
标题翻译：发光二极管封装及其制造方法
公开(公告)号：US20070063214A1
公开(公告)日：2007-03-22
申请号：US11524278
申请日：2006-09-21
申请人： Yong Kim , Seog Choi , Chang Lim , Yong Kim
发明人： Yong Kim , Seog Choi , Chang Lim , Yong Kim
IPC分类号： H01L33/00
CPC分类号： H01L33/507 , H01L33/58
摘要： The invention relates to a light emitting diode package that can prevent deterioration of phosphor and a method of manufacturing the same. The light emitting diode package includes a package body having a recessed part, a light emitting diode chip mounted on a floor surface of the recessed part and a lens structure disposed on an upper surface of the package body, apart from the light emitting diode chip. Phosphor is dispersed in at least a part of the lens structure.
摘要翻译：本发明涉及能够防止荧光体劣化的发光二极管封装及其制造方法。发光二极管封装包括具有凹部的封装主体，安装在凹部的地板表面上的发光二极管芯片和设置在封装体的上表面上的透镜结构，与发光二极管芯片分开。荧光体分散在透镜结构的至少一部分中。

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