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1. 发明授权

US06507527B1 Memory line discharge before sensing 有权
标题翻译：感应前存储线放电
公开(公告)号：US06507527B1
公开(公告)日：2003-01-14
申请号：US09698614
申请日：2000-10-27
申请人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
发明人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/12
摘要： A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.
摘要翻译：一种通过将数据线从高于期望电压电平的电压电平放电到大约期望的电压电平，在数据线在低功率存储器件中被感测之前将数据线充电到期望的电压电平的方法。通过使用N型晶体管将数据线放电至期望的电压电平，可以用更便宜的组件更快地达到电压电平。

2. 发明授权

US06347052B1 Word line decoding architecture in a flash memory 有权
标题翻译：字线解码架构在闪存中
公开(公告)号：US06347052B1
公开(公告)日：2002-02-12
申请号：US09690554
申请日：2000-10-17
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C8/10
摘要： A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.
摘要翻译：描述了具有字线解码和选择架构的闪速存储器。闪速存储器包括存储单元的第一和第二扇区，第一和第二本地驱动电路，第一，第二和第三解码电路以及驱动电路。第一存储器单元的第一扇区包括耦合到第一存储器单元的第一多个字线，每个字线能够是第一选定的字线。第二存储器单元的第二扇区包括类似的局部驱动器电路独立地耦合到第一扇区的第一和第二多个字线的每个字线。每个解码电路包括解码电路的第一和第二侧。解码电路的第一侧激活第一选定的多个本地驱动器电路，并且解码电路的第二侧激活第二选定的多个局部驱动器电路。第二解码电路耦合到第一本地驱动电路，并将第一升压电压提供给耦合到第一本地驱动电路的第一选定字线。第三解码电路耦合到第二本地驱动电路，并将第二升压电压提供给第二选定字线。驱动电路向第一解码电路，第二解码电路，第三解码电路，第一本地驱动电路和第二本地驱动电路提供一系列升压电压。

3. 发明授权

US06229735B1 Burst read mode word line boosting 有权
标题翻译：突发读取模式字线提升
公开(公告)号：US06229735B1
公开(公告)日：2001-05-08
申请号：US09638055
申请日：2000-08-11
申请人： Takao Akaogi , Kendra Nguyen , Yong Kim , Lee Cleveland
发明人： Takao Akaogi , Kendra Nguyen , Yong Kim , Lee Cleveland
IPC分类号： G11C1606
CPC分类号： G11C8/18 , G11C8/08
摘要： A burst read mode operation is provided that boosts the voltage of a word line while the bit lines of the row are selected for reading. When the column group address bits read the last column group of cells in the row, a pulse signal is generated which temporarily reduces the boosted voltage to allow the X-decoder to select the next word line. An alternative delay element is also provided which generates an ATD pulse with a longer duration when the column group address bits are at the end of a row and a shorter duration pulse at other times.
摘要翻译：提供突发读取模式操作，其提高字线的电压，同时选择行的位线用于读取。当列组地址位读取行中的最后一列单元格时，产生脉冲信号，临时降低升压电压，以允许X解码器选择下一个字线。还提供了另一种延迟元件，当列组地址位在行的末尾，而在其他时间具有较短的持续时间脉冲时，其产生具有较长持续时间的ATD脉冲。

4. 发明授权

US06621761B2 Burst architecture for a flash memory 有权
公开(公告)号：US06621761B2
公开(公告)日：2003-09-16
申请号：US09829518
申请日：2001-04-09
申请人： Takao Akaogi , Lee Cleveland , Kendra Nguyen
发明人： Takao Akaogi , Lee Cleveland , Kendra Nguyen
IPC分类号： G06C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit, a control circuit coupled to the first circuit, and a data buffer selectively coupled to the first circuit by the control circuit. The first circuit accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal. The data buffer has an output and produces the first data word at the output and successively produces, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output. The subsequent data words correspond to the subsequent accesses of the plurality of data words.

5. 发明授权

US06243316B1 Voltage boost reset circuit for a flash memory 有权
标题翻译：闪存的升压复位电路
公开(公告)号：US06243316B1
公开(公告)日：2001-06-05
申请号：US09501159
申请日：2000-02-09
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/08
摘要： A voltage boost circuit (111) for a memory (100) includes a boosting circuit (110) which is coupled to a boosted node (120) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (112) coupled to the boosted node and including a switchable zero-threshold transistor (202) for resetting the boosted node to a reset voltage (VCC).
摘要翻译：用于存储器（100）的升压电路（111）包括升压电路（110），其被耦合到升压节点（120）以升高用于访问存储器的核心单元的字线电压。升压电路还包括耦合到升压节点的复位电路（112），并且包括用于将升压节点复位到复位电压（VCC）的可切换零阈值晶体管（202）。

6. 发明授权

US06351420B1 Voltage boost level clamping circuit for a flash memory 有权
标题翻译：用于闪存的电压升压电平钳位电路
公开(公告)号：US06351420B1
公开(公告)日：2002-02-26
申请号：US09595519
申请日：2000-06-16
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/12 , G11C16/30
摘要： A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.
摘要翻译：用于闪存（100）的升压电路（111）包括升压电路（110），其能够将闪存的电源电压（VCC）的一部分升压到足以访问的字线电压电平存储器的核心单元阵列（102）中的核心单元。升压电路还包括用于向升压电路提供非零调节电压（VCL）的平衡或钳位电路（112），以在电源电压超过时减小升压电路可用于升压的电源电压部分一定的价值。

7. 发明授权

US06240040B1 Multiple bank simultaneous operation for a flash memory 有权
标题翻译：多存储银行同时操作闪存
公开(公告)号：US06240040B1
公开(公告)日：2001-05-29
申请号：US09526239
申请日：2000-03-15
申请人： Takao Akaogi , Lee Edward Cleveland , Kendra Nguyen
发明人： Takao Akaogi , Lee Edward Cleveland , Kendra Nguyen
IPC分类号： G11C800
CPC分类号： G11C16/26 , G11C16/08 , G11C16/10 , G11C2216/22
摘要： An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-1 banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals. The address buffer circuitry is used to simultaneously provide a write address and a read address in order to access core memory cells. Respective first portions of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals. Respective second portions of the write and read addresses are provided to the respective address selection circuit.
摘要翻译：描述了用于多组（或N组）同时操作闪速存储器的地址缓冲和解码架构。对于在N个存储体的一个存储体中的读取操作的持续时间，只能对其他N-1个存储体中的任一个进行写入操作。对于在N个存储体的一个存储体中的写入操作的持续时间，只能对其他N-1个存储体中的任一个进行读取操作。地址缓冲和解码架构包括控制逻辑电路，位于N个存储体中的每一个的地址选择电路和地址缓冲器电路。控制逻辑电路用于产生N个读取选择信号以选择用于读取操作的N个存储体中的一个存储单元和N个写入选择信号，以便为写入操作选择N个存储体的另一个存储体。每个地址选择电路被配置为从控制逻辑电路接收N个读选择信号中的相应一个和N个写入选择信号中的相应一个。地址缓冲器电路用于同时提供写入地址和读取地址以便访问核心存储器单元。将写入和读取地址的各个第一部分提供给控制逻辑电路以产生相应的N个读取选择信号和N个写入选择信号。将写入和读取地址的相应第二部分提供给相应的地址选择电路。

8. 发明授权

US06611473B2 Power-saving modes for memories 失效
公开(公告)号：US06611473B2
公开(公告)日：2003-08-26
申请号：US10061620
申请日：2002-02-01
申请人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
发明人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
IPC分类号： G11C700
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/1072 , G11C2207/2263
摘要： A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

9. 发明授权

US06400633B1 Power-saving modes for memories 有权
公开(公告)号：US06400633B1
公开(公告)日：2002-06-04
申请号：US09675372
申请日：2000-09-29
申请人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
发明人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
IPC分类号： G11C700
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/1072 , G11C2207/2263
摘要： A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

10. 发明授权

US07227768B2 Power interconnect structure for balanced bitline capacitance in a memory array 有权
标题翻译：用于存储器阵列中平衡位线电容的功率互连结构
公开(公告)号：US07227768B2
公开(公告)日：2007-06-05
申请号：US11173930
申请日：2005-07-01
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C5/06
CPC分类号： H01L23/5286 , H01L23/5222 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure situated over the memory core array, where the interconnect structure is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines. The interconnect structure can include at least one interconnect line, which can form an angle with respect to the bitlines that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure can form one of a number of capacitances with each of the bitlines, where each of the capacitances can be substantially equal in value to each other of the capacitances.
摘要翻译：根据一个示例性实施例，半导体管芯包括位于衬底上的存储器芯阵列，其中存储器芯阵列包括多个位线，其中位线可以位于半导体管芯中的第一互连金属层中。半导体管芯还包括位于存储器芯阵列上方的互连结构，其中互连结构位于半导体管芯中的第二互连金属层中并且位于每个位线上。互连结构可以包括至少一个互连线，其可以相对于位线形成可以大于0.0度且小于或等于90.0度的角度。互连结构可以形成与每个位线的多个电容中的一个，其中每个电容可以在电容中彼此的值基本相等。

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