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1. 发明授权

US06507527B1 Memory line discharge before sensing 有权
标题翻译：感应前存储线放电
公开(公告)号：US06507527B1
公开(公告)日：2003-01-14
申请号：US09698614
申请日：2000-10-27
申请人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
发明人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/12
摘要： A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.
摘要翻译：一种通过将数据线从高于期望电压电平的电压电平放电到大约期望的电压电平，在数据线在低功率存储器件中被感测之前将数据线充电到期望的电压电平的方法。通过使用N型晶体管将数据线放电至期望的电压电平，可以用更便宜的组件更快地达到电压电平。

2. 发明授权

US06400633B1 Power-saving modes for memories 有权
公开(公告)号：US06400633B1
公开(公告)日：2002-06-04
申请号：US09675372
申请日：2000-09-29
申请人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
发明人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
IPC分类号： G11C700
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/1072 , G11C2207/2263
摘要： A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

3. 发明授权

US06611473B2 Power-saving modes for memories 失效
公开(公告)号：US06611473B2
公开(公告)日：2003-08-26
申请号：US10061620
申请日：2002-02-01
申请人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
发明人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
IPC分类号： G11C700
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/1072 , G11C2207/2263
摘要： A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

4. 发明授权

US06396749B2 Dual-ported CAMs for a simultaneous operation flash memory 有权
标题翻译：双端口CAM用于同时运行的闪存
公开(公告)号：US06396749B2
公开(公告)日：2002-05-28
申请号：US09829657
申请日：2001-04-10
申请人： Ali Al-Shamma , Lee Cleveland
发明人： Ali Al-Shamma , Lee Cleveland
IPC分类号： G11C700
CPC分类号： G11C29/789 , G11C8/16 , G11C15/046
摘要： A flash memory having redundancy content addressable memory (CAM) circuitry is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array of memory cells, a redundant array of memory cells, and the redundancy CAM circuitry. The redundancy CAM circuitry includes a plurality of dual-ported CAM stages. Each CAM stage includes a CAM cell, a write data bus coupled to the CAM cell, and a read data bus coupled to the CAM cell. The CAM cell stores information regarding a location of an inoperative memory cell in the primary array. The inoperative memory cell requires a substitution with a second memory cell in the redundant array. The write data bus produces the information from the CAM cell responsively to a write select signal. The write select signal is indicative of a write operation to be performed at memory cell locations in the primary array. The read data bus produces the information from the CAM cell responsively to a read select signal. The read select signal is indicative of a read operation to be performed at memory cell locations in the primary array.
摘要翻译：描述具有冗余内容可寻址存储器（CAM）电路的闪速存储器。闪存能够将第二存储器单元替换为不工作的存储单元。闪速存储器包括存储器单元的主阵列，存储器单元的冗余阵列和冗余CAM电路。冗余CAM电路包括多个双端口CAM级。每个CAM阶段包括CAM单元，耦合到CAM单元的写数据总线以及耦合到CAM单元的读数据总线。 CAM单元存储关于主阵列中的不工作存储单元的位置的信息。不工作的存储单元需要用冗余阵列中的第二个存储单元进行替换。写数据总线响应于写选择信号产生来自CAM单元的信息。写入选择信号指示要在主阵列中的存储器单元位置处执行的写入操作。读取数据总线响应于读取选择信号产生来自CAM单元的信息。读取选择信号指示要在主阵列中的存储器单元位置处执行的读取操作。

5. 发明授权

US06621761B2 Burst architecture for a flash memory 有权
公开(公告)号：US06621761B2
公开(公告)日：2003-09-16
申请号：US09829518
申请日：2001-04-09
申请人： Takao Akaogi , Lee Cleveland , Kendra Nguyen
发明人： Takao Akaogi , Lee Cleveland , Kendra Nguyen
IPC分类号： G06C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit, a control circuit coupled to the first circuit, and a data buffer selectively coupled to the first circuit by the control circuit. The first circuit accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal. The data buffer has an output and produces the first data word at the output and successively produces, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output. The subsequent data words correspond to the subsequent accesses of the plurality of data words.

6. 发明授权

US06347052B1 Word line decoding architecture in a flash memory 有权
标题翻译：字线解码架构在闪存中
公开(公告)号：US06347052B1
公开(公告)日：2002-02-12
申请号：US09690554
申请日：2000-10-17
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C8/10
摘要： A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.
摘要翻译：描述了具有字线解码和选择架构的闪速存储器。闪速存储器包括存储单元的第一和第二扇区，第一和第二本地驱动电路，第一，第二和第三解码电路以及驱动电路。第一存储器单元的第一扇区包括耦合到第一存储器单元的第一多个字线，每个字线能够是第一选定的字线。第二存储器单元的第二扇区包括类似的局部驱动器电路独立地耦合到第一扇区的第一和第二多个字线的每个字线。每个解码电路包括解码电路的第一和第二侧。解码电路的第一侧激活第一选定的多个本地驱动器电路，并且解码电路的第二侧激活第二选定的多个局部驱动器电路。第二解码电路耦合到第一本地驱动电路，并将第一升压电压提供给耦合到第一本地驱动电路的第一选定字线。第三解码电路耦合到第二本地驱动电路，并将第二升压电压提供给第二选定字线。驱动电路向第一解码电路，第二解码电路，第三解码电路，第一本地驱动电路和第二本地驱动电路提供一系列升压电压。

7. 发明授权

US06229735B1 Burst read mode word line boosting 有权
标题翻译：突发读取模式字线提升
公开(公告)号：US06229735B1
公开(公告)日：2001-05-08
申请号：US09638055
申请日：2000-08-11
申请人： Takao Akaogi , Kendra Nguyen , Yong Kim , Lee Cleveland
发明人： Takao Akaogi , Kendra Nguyen , Yong Kim , Lee Cleveland
IPC分类号： G11C1606
CPC分类号： G11C8/18 , G11C8/08
摘要： A burst read mode operation is provided that boosts the voltage of a word line while the bit lines of the row are selected for reading. When the column group address bits read the last column group of cells in the row, a pulse signal is generated which temporarily reduces the boosted voltage to allow the X-decoder to select the next word line. An alternative delay element is also provided which generates an ATD pulse with a longer duration when the column group address bits are at the end of a row and a shorter duration pulse at other times.
摘要翻译：提供突发读取模式操作，其提高字线的电压，同时选择行的位线用于读取。当列组地址位读取行中的最后一列单元格时，产生脉冲信号，临时降低升压电压，以允许X解码器选择下一个字线。还提供了另一种延迟元件，当列组地址位在行的末尾，而在其他时间具有较短的持续时间脉冲时，其产生具有较长持续时间的ATD脉冲。

8. 发明申请

US20070070610A1 Low profile autodocking multi-battery pack system and in place service PCI storage controller card with redundant cache and concurrently maintainable redundant battery backup 有权
标题翻译：低调自动封锁多电池组系统，并配备了具有冗余缓存和同时维护冗余电池备份的PCI存储控制器卡
公开(公告)号：US20070070610A1
公开(公告)日：2007-03-29
申请号：US11239599
申请日：2005-09-29
申请人： Lee Cleveland , Eric Eckberg , Jeffery Gathje , Michael Good , Herbert Jensen , Mark Pfeifer , John Skurdalsvold
发明人： Lee Cleveland , Eric Eckberg , Jeffery Gathje , Michael Good , Herbert Jensen , Mark Pfeifer , John Skurdalsvold
IPC分类号： H05K5/00
CPC分类号： G06F1/263 , G06F1/184 , G06F1/185 , G06F1/186 , G06F1/188 , G06F11/1666 , G06F11/2015
摘要： A low profile auto docking multi-battery pack system and an in place service PCI storage controller card system with redundant cache and concurrently maintainable redundant battery backup are provided. A first battery and a second battery are disposed in line to provide a low profile battery pack. The first battery and second battery are shrink-wrapped together inside a frame and are slideably removable through an opening in a PCI tailstock and are hot swappable. The PCI storage controller card system is defined by a two card assembly that includes an internal connector, such as a SCSI connector to connect the two cards together.
摘要翻译：提供了一个低调的自动对接多电池组系统和一个就绪的服务PCI存储控制器卡系统与冗余缓存和同时可维护的冗余电池备份。第一电池和第二电池被排列成一行以提供低轮廓的电池组。第一个电池和第二个电池在一个框架内收缩包装在一起，并且可以通过PCI尾座的开口可滑动地拆卸，并且是可热插拔的。 PCI存储控制器卡系统由包括内部连接器的两个卡组件来定义，诸如将两个卡连接在一起的SCSI连接器。

9. 发明授权

US06798275B1 Fast, accurate and low power supply voltage booster using A/D converter 有权
标题翻译：使用A / D转换器的快速，准确和低电源电压升压器
公开(公告)号：US06798275B1
公开(公告)日：2004-09-28
申请号：US10406415
申请日：2003-04-03
申请人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
发明人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
IPC分类号： G05F110
CPC分类号： G11C5/145 , G11C8/08
摘要： Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.
摘要翻译：公开了闪存阵列系统和方法，用于产生用于读取操作的稳压升压字线电压。该系统包括多级升压电路，其可操作以从电源电压检测电路接收电源电压和一个或多个输出信号，以产生具有大于电源电压的值的升压字线电压。升压电路包括预充电电路和连接到升压字线的公共节点的多个升压单元以及定时控制电路。多个升压单元的级级串联耦合，用于级之间的电荷共享，并且将预定数量的升压单元耦合到升压字线公共节点，以在预升压定时期间向升压的字线提供中间电压从而预期在升压定时期间提供的最后升高的字线电压。电压升压电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于一个或多个输出信号改变多级升压电路的升压增益，从而使升压的字线电压基本上不依赖于电源电压值。

10. 发明授权

US06765827B1 Method and system for detecting defective material surrounding flash memory cells 有权
标题翻译：用于检测闪存单元周围的有缺陷的材料的方法和系统
公开(公告)号：US06765827B1
公开(公告)日：2004-07-20
申请号：US10384936
申请日：2003-03-10
申请人： Jiang Li , Lee Cleveland , Ming Kwan
发明人： Jiang Li , Lee Cleveland , Ming Kwan
IPC分类号： G11C1606
CPC分类号： H01L29/66825 , G11C16/04 , G11C29/50
摘要： In a method and system for detecting defective material surrounding a flash memory cell, stressing voltage is applied between a control gate and a well of the flash memory cell. A stress recovery process is then performed on the flash memory cell. Any short circuit, formed through the material between the control gate and at least one of drain and source bit line junctions of the flash memory cell, is detected. The material surrounding the flash memory cell may be an inter-level dielectric material. The present invention may be applied to an array of flash memory cells comprising a flash memory device during testing of the flash memory device before being shipped to the customer.
摘要翻译：在用于检测闪存单元周围的有缺陷的材料的方法和系统中，在闪存单元的控制栅极和阱之间施加施加电压。然后在闪存单元上进行应力恢复处理。检测到通过控制栅极与闪存单元的漏极和源极位线之间的材料形成的任何短路。围绕闪存单元的材料可以是层间电介质材料。本发明可以应用于在被发送给客户之前在闪速存储器件的测试期间包括闪存器件的闪存单元的阵列。

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