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1. 发明授权

US08015389B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08015389B2
公开(公告)日：2011-09-06
申请号：US12000953
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

2. 发明授权

US07774577B2 Memory device, memory controller and memory system 有权
公开(公告)号：US07774577B2
公开(公告)日：2010-08-10
申请号：US12000952
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12 , G06F12/04
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

3. 发明授权

US07722107B2 Vehicular center cluster panel 失效
标题翻译：车载中心集群板
公开(公告)号：US07722107B2
公开(公告)日：2010-05-25
申请号：US12216621
申请日：2008-07-08
申请人： Takahiko Sato , Masanobu Tomida , Shigeru Yabuya , Kiyoshi Suenaga
发明人： Takahiko Sato , Masanobu Tomida , Shigeru Yabuya , Kiyoshi Suenaga
IPC分类号： B60J7/00
CPC分类号： B60K37/00 , B60K2350/925
摘要： A center cluster panel 2 is formed with a projected portion 20 including an upper panel 21 extended to a vehicle rear side and disposed at an uppermost portion thereof, a curved face panel 22 connected to a rear portion of the upper panel 21 and directed to a vehicle front side by being bent from the connected portion 24, and a lower panel 23 connected to the curved face panel 22, extended to a front side and disposed on a vehicle lower side of the upper panel 21. The upper panel 21 and the lower panel 23 are formed such that respective wall thicknesses t1 and t2 are uniform. The wall thickness t1 of the upper panel 21 is made to be thicker than the wall thickness t2 of the lower panel 23. The curved face panel 22 is formed such that a wall thickness t3 thereof is equal to the wall thickness t1 of the upper panel 21 at the portion 24 connected with the upper panel 21 and formed such that the more proximate to the lower panel 23 from the connected portion 24, the more thinned the wall thickness t3 gradually.
摘要翻译：中心集束板2形成有突出部20，突出部20包括延伸到车辆后侧并设置在其最上部的上板21，连接到上板21的后部并指向一个车辆前侧通过从连接部分24弯曲而连接的下面板23和连接到弯曲面板22的下面板23延伸到前侧并设置在上板21的车辆下侧上。上板21和下板板23形成为使各壁厚t1和t2均匀。使上板21的壁厚t1比下板23的壁厚t2厚。弯曲面板22的壁厚t3与上板的壁厚t1相同如图21所示，在与上板21连接的部分24处，并且形成为使得从连接部分24越接近下板23，逐渐减薄壁厚度t3。

4. 发明申请

US20090089493A1 SEMICONDUCTOR MEMORY, OPERATING METHOD OF SEMICONDUCTOR MEMORY, AND SYSTEM 有权
标题翻译：半导体存储器，半导体存储器的操作方法和系统
公开(公告)号：US20090089493A1
公开(公告)日：2009-04-02
申请号：US12235353
申请日：2008-09-22
申请人： Hitoshi IKEDA , Takahiko Sato , Tomohiro Kawakubo
发明人： Hitoshi IKEDA , Takahiko Sato , Tomohiro Kawakubo
IPC分类号： G06F12/06
CPC分类号： G11C11/4076 , G11C7/1042
摘要： Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside.
摘要翻译：操作控制电路响应于第一操作命令开始任何存储器核心的第一操作，响应于第二操作命令开始任何存储器核心的第二操作，并终止第一操作并且响应于继续执行第二操作以终止多个存储器核的操作的终止命令。例如，半导体存储器与访问半导体存储器的控制器一起安装在系统上。根据存储器核心的操作状态来判断响应于终止命令的操作的终止。因此，可以在不从外部指定存储器核心的情况下终止需要终止操作的存储器芯的操作。

5. 发明申请

US20070202986A1 Roller bearing for planetary gear mechanism 审中-公开
标题翻译：用于行星齿轮机构的滚子轴承
公开(公告)号：US20070202986A1
公开(公告)日：2007-08-30
申请号：US11706432
申请日：2007-02-15
申请人： Kazuyuki Kotani , Kazunao Saito , Takahiko Sato , Hiroshi Sato
发明人： Kazuyuki Kotani , Kazunao Saito , Takahiko Sato , Hiroshi Sato
IPC分类号： F16H57/08
CPC分类号： F16C33/543 , F16C19/466 , F16C33/4605 , F16C2240/70 , F16C2361/61 , F16H57/082 , F16H2057/085
摘要： A roller bearing (needle roller bearing) of the cage-and-roller type for a planetary gear mechanism includes a plurality of rollers (needle rollers), and a cage positioning and holding these rollers, and an outside diameter surface of the cage is guided by a bore diameter surface of a planetary gear. An outside diameter dimension of the cage is set to a value which is not smaller than 95% and not larger than 97% of an inner diameter dimension of the planetary gear.
摘要翻译：用于行星齿轮机构的保持架和滚轮式的滚子轴承（滚针轴承）包括多个滚子（滚针）和定位并保持这些滚子的保持架，并且保持架的外径表面被引导通过行星齿轮的孔径表面。保持架的外径尺寸设定为不小于行星齿轮的内径尺寸的95％且不大于97％的值。

6. 发明申请

US20050099850A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20050099850A1
公开(公告)日：2005-05-12
申请号：US10826253
申请日：2004-04-19
申请人： Takahiko Sato
发明人： Takahiko Sato
IPC分类号： G11C11/409 , G11C7/10 , G11C11/403 , G11C7/00
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078 , G11C7/1093
摘要： A memory device is provided, which includes a data receive gate to buffer, in a first buffer, data to be inputted, a data transfer gate to input the data of the first buffer and buffer the same data in a second buffer, a data write gate to output the data of the second buffer to a data bus, and a memory cell to write and store the data in the data bus. In a control circuit thereof, data is not inputted to the first buffer by controlling the data receive gate and at the same time data is inputted to the second buffer by controlling the data transfer gate, depending on a time period from activation of a write enable signal to changing of a data mask signal.
摘要翻译：提供了一种存储装置，其包括：数据接收门，用于在第一缓冲器中缓冲要输入的数据;数据传输门，用于输入第一缓冲器的数据并在第二缓冲器中缓冲相同的数据;数据写入门将第二缓冲器的数据输出到数据总线，以及存储器单元，用于将数据写入并存储在数据总线中。在其控制电路中，通过控制数据接收门而不将数据输入到第一缓冲器，并且同时通过控制数据传送门将数据输入到第二缓冲器，这取决于写入使能的激活时间信号改变数据掩码信号。

7. 发明申请

US20090215378A1 Air-conditioning duct system 审中-公开
标题翻译：空调管道系统
公开(公告)号：US20090215378A1
公开(公告)日：2009-08-27
申请号：US12379502
申请日：2009-02-24
申请人： Nobuhiro Terai , Takahiko Sato , Shintaro Okawa , Katsuhiro Katagiri
发明人： Nobuhiro Terai , Takahiko Sato , Shintaro Okawa , Katsuhiro Katagiri
IPC分类号： B60H1/34
CPC分类号： B60H1/3428 , B60H2001/3478
摘要： An outer tube part 8 and an inner tube part 6 which is disposed in an interior of the outer tube part 8 are provided in an air-conditioning duct system which is connected to an air flow path downstream side of a vehicle air-conditioning system, and a side branch type silencer chamber 9 is defined by an inner circumferential surface of the outer tube part 8 and an outer circumferential surface of the inner tube part 6. In addition, an axis of at least a portion of the outer tube part 8 which confronts the inner tube part 6 and an axis of the inner tube part 6 are both made to be a straight line, and a register functioning part is provided in an interior of a portion of the outer tube part 8 which lies further downstream in an air flow path than the inner tube part 6.
摘要翻译：设置在外管部8的内部的外管部8和内管部6设置在与车辆空调系统的空气流路下游侧连接的空调管道系统中，侧管式消音器室9由外管部8的内周面和内管部6的外周面形成。此外，外管部8的至少一部分的轴线内管部分6面对的内管部分6的轴线都被制成直线，并且在外管部分8的位于空气进一步下游的部分的内部设有对准功能部分流路比内管部分6。

8. 发明授权

US07471585B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US07471585B2
公开(公告)日：2008-12-30
申请号：US11508917
申请日：2006-08-24
申请人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
发明人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
IPC分类号： G11C7/00
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/02 , G11C29/50012 , G11C29/50016 , G11C2029/0403 , G11C2211/4061
摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.
摘要翻译：响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。刷新操作在访问请求与刷新请求之间发生冲突时结束。因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。结果，可以减少半导体存储器的显影周期。

9. 发明申请

US20080146139A1 Low-profile air conditioning register 审中-公开
标题翻译：低调的空调寄存器
公开(公告)号：US20080146139A1
公开(公告)日：2008-06-19
申请号：US11987038
申请日：2007-11-27
申请人： Nobuhiro Terai , Minoru Shibata , Takahiko Sato
发明人： Nobuhiro Terai , Minoru Shibata , Takahiko Sato
IPC分类号： B60H1/34
CPC分类号： B60H1/3421 , B60H2001/3471
摘要： A low-profile air conditioning register is provided with a retainer, a bezel and a plurality of downstream fins. The bezel is arranged in such a manner as to position a lower long side of an opening of a passage portion in a downstream than an upper long side. The angle formed between a flange portion and the ventilation direction of the retainer is equal to or more than 60°. Further, the length of a corresponding line to a short side of the opening in a surface which is orthogonal to the ventilation direction is equal to or less than 35 mm. Further a lower inner wall in the passage portion is inclined with respect to the ventilation direction in such a manner as to become lower toward a downstream side. The lower inner wall surface has a length equal to or less than 10 mm along a thickness direction of the flange portion.
摘要翻译：低调空调装置设置有保持器，挡板和多个下游翅片。挡板布置成使得通道部分的开口的下长边位于比上长边的下游位置。在凸缘部分和保持器的通气方向之间形成的角度等于或大于60°。此外，与通气方向正交的表面中的开口的短边的对应线的长度等于或小于35mm。此外，通道部分中的下部内壁相对于通气方向倾斜，朝向下游侧变低。下部内壁面沿凸缘部的厚度方向的长度为10mm以下。

10. 发明授权

US07113441B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07113441B2
公开(公告)日：2006-09-26
申请号：US11057841
申请日：2005-02-15
申请人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
发明人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
IPC分类号： G11C7/00
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/02 , G11C29/50012 , G11C29/50016 , G11C2029/0403 , G11C2211/4061
摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.
摘要翻译：响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。刷新操作在访问请求与刷新请求之间发生冲突时结束。因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。结果，可以减少半导体存储器的显影周期。

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