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1. 发明授权

US6004701A Method for designing Levenson photomask 失效
标题翻译：设计Levenson光掩模的方法
公开(公告)号：US6004701A
公开(公告)日：1999-12-21
申请号：US46794
申请日：1998-03-24
申请人： Taiga Uno , Kiyomi Koyama , Kazuko Yamamoto , Satoshi Tanaka , Sachiko Kobayashi , Koji Hashimoto
发明人： Taiga Uno , Kiyomi Koyama , Kazuko Yamamoto , Satoshi Tanaka , Sachiko Kobayashi , Koji Hashimoto
IPC分类号： G03F1/30 , G03F1/68 , H01L21/027 , G03F9/00 , G06F17/50
CPC分类号： G03F1/30
摘要： In a Levenson photomask design method of partially forming a plurality of opening patterns for passing incident light in a light-shielding film for shielding the incident light, and arranging, on some patterns, phase shifters, line segment pairs of different patterns which are adjacent to each other within a predetermined distance R are extracted in units of line segments obtained by dividing the patterns. A pattern within a predetermined distance S from the central point of the opposite region of a line segment pair of interest in a direction perpendicular to the line segments is obtained. The obtained pattern is subjected to a process simulation to obtain resolution easiness representing the easiness in resolving the adjacent patterns. On the basis of the resolution easiness obtained for the adjacent pattern pair within the distance R, a phase shifter is arranged in ascending order of resolution easiness to give a phase difference. Resolution suitable for the exposure condition used can be obtained by a simple method. When the shifter arrangement is determined in consideration of the resolution easiness, a high-resolution shifter arrangement can be realized for a Levenson phase shift mask.
摘要翻译：在莱文森光掩模设计方法中，部分地形成用于使入射光入射到遮光膜中的入射光的多个开口图案，用于屏蔽入射光，并且在某些图案上布置移相器，与不同图案相邻的线段对以规定的距离R为单位，以通过划分图案而得到的线段为单位提取。获得与垂直于线段的方向相关的线段对的相对区域的中心点的预定距离S内的图案。对所获得的图案进行处理模拟以获得表示分辨相邻图案的容易性的分辨率容易度。基于在距离R内对相邻图案对获得的分辨率容易度，移位器按分辨率的顺序排列顺序排列以给出相位差。可以通过简单的方法获得适合于所使用的曝光条件的分辨率。考虑到分辨率容易度来确定移位器装置时，可以实现对莱文森相移掩模的高分辨率移位器装置。

2. 发明授权

US06243855B1 Mask data design method 有权
标题翻译：进行自动校正处理
公开(公告)号：US06243855B1
公开(公告)日：2001-06-05
申请号：US09161959
申请日：1998-09-29
申请人： Sachiko Kobayashi , Taiga Uno , Kazuko Yamamoto , Koji Hashimoto
发明人： Sachiko Kobayashi , Taiga Uno , Kazuko Yamamoto , Koji Hashimoto
IPC分类号： G06F760
CPC分类号： G03F7/70441 , G03F1/36
摘要： A correction target segment extracted from the design pattern is divided into lengths suited for correction. If the arrangement of the divided segments is a one-dimensional pattern, a correction value is obtained by conducting a one-dimensional process simulation to an arrangement within a predetermined distance from a divided segment in perpendicular direction. If the arrangement of the divided segments is a two-dimensional pattern, a correction value is obtained by two-dimensionally extracting a pattern included in a rectangular region having a predetermined distance from one point on the divided segment in perpendicular and horizontal directions and by conducting a two-dimensional process simulation to the extracted pattern.
摘要翻译：从设计图案提取的校正目标片段被划分为适合于校正的长度。如果分割段的排列是一维图案，则通过对垂直方向上的分割段的预定距离内的排列进行一维处理模拟来获得校正值。如果分割的片段的排列是二维图案，则通过二维地提取包括在具有预定距离的矩形区域中的图案，从而在垂直和水平方向上分割片段上的一个点，并且通过导线对提取的图案进行二维过程模拟。

3. 发明授权

US6060368A Mask pattern correction method 失效
标题翻译：掩模图案校正方法和系统
公开(公告)号：US6060368A
公开(公告)日：2000-05-09
申请号：US206364
申请日：1998-12-07
申请人： Koji Hashimoto , Hisako Aoyama , Soichi Inoue , Kazuko Yamamoto , Sachiko Kobayashi
发明人： Koji Hashimoto , Hisako Aoyama , Soichi Inoue , Kazuko Yamamoto , Sachiko Kobayashi
IPC分类号： G03F1/36 , G03F1/72 , G03F7/20 , H01L21/027 , H01L21/76
CPC分类号： G03F7/70441 , G03F1/36
摘要： This invention is provided to eliminate the optical proximity effect which will occur because of different rates of dimensional change between before and after etching when a plurality of gate materials are etched in a single device. After a to-be-corrected region is extracted, an n.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the n.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be a p.sup.+ -type polysilicon gate layer, thereby correcting the size of the n.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the n.sup.+ -type polysilicon gate layer. After that, a p.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the p.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be an n.sup.+ -type polysilicon gate layer, thereby correcting the size of the p.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the p.sup.+ -type polysilicon gate layer.
摘要翻译：提供本发明以消除当在单个器件中蚀刻多个栅极材料时在蚀刻之前和之后不同的尺寸变化率而将发生的光学邻近效应。在提取待校正区域之后，提取n +型多晶硅栅极层。然后，从n +型多晶硅栅极层到可以是p +型多晶硅栅极层的与其相邻的图案计算距离，从而参照n +型多晶硅栅极层的校正表来校正n +型多晶硅栅极层的尺寸图案与n +型多晶硅栅极层相邻。之后，提取p +型多晶硅栅极层。然后，从p +型多晶硅栅极层到与其相邻的图案，其可以是n +型多晶硅栅极层，从而根据用于的p +型多晶硅栅极层的校正表来校正p +型多晶硅栅极层的尺寸，图案与p +型多晶硅栅极层相邻。

4. 发明授权

US5538815A Method for designing phase-shifting masks with automatization capability 失效
标题翻译：设计具有自动化功能的相移掩模的方法
公开(公告)号：US5538815A
公开(公告)日：1996-07-23
申请号：US120386
申请日：1993-09-14
申请人： Kazuko Oi , Shigehiro Hara , Kiyomi Koyama , Koji Hashimoto , Shinichi Ito , Katsuya Okumura
发明人： Kazuko Oi , Shigehiro Hara , Kiyomi Koyama , Koji Hashimoto , Shinichi Ito , Katsuya Okumura
IPC分类号： G03F1/28 , G03F9/00
CPC分类号： G03F1/28
摘要： A method for designing a phase-shifting mask in a manner that a phase shifter of the mask is arranged so that a phase difference between light transmitted through clear areas with the phase shifter and light transmitted through clear areas without the phase shifter is set to 180.degree. or further different combination of phase differences being such as 0.degree., 90.degree. and 270.degree.. The method includes the steps of: defining a threshold value in a manner that the threshold value falls within a range which is possible to resolve using the phase-shifting masks; measuring a distance between neighboring shapes of the clear area; storing adjacent relationship of the neighboring shapes whose distance is less than the threshold; and automatically placing the phase shifter on one of the neighboring shapes of the clear areas in a manner that mutually neighboring clear area have an opposite phase to each other.
摘要翻译：一种用于以掩模的移相器的方式设计移相掩模的方法，使得透过透过区域的光与移相器之间的相位差和透过透明区域而没有移相器的光被设置为180° DEG或相差的其他不同组合如0°，90°和270°。该方法包括以下步骤：以阈值落在可以使用相移掩模解析的范围内的方式定义阈值; 测量透明区域的相邻形状之间的距离; 存储距离小于阈值的相邻形状的相邻关系; 并且以相互相邻的清除区域彼此具有相反的相位的方式自动地将移相器放置在透明区域的相邻形状中的一个上。

5. 发明授权

US08142961B2 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 有权
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US08142961B2
公开(公告)日：2012-03-27
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

6. 发明申请

US20120070767A1 SET OF MASKS, METHOD OF GENERATING MASK DATA AND METHOD FOR FORMING A PATTERN 有权
标题翻译：一套掩模，生成掩模数据的方法和形成图案的方法
公开(公告)号：US20120070767A1
公开(公告)日：2012-03-22
申请号：US13289099
申请日：2011-11-04
申请人： Satoshi Tanaka , Koji Hashimoto
发明人： Satoshi Tanaka , Koji Hashimoto
IPC分类号： G03F1/36
CPC分类号： H01L21/0274 , G03F1/70 , G06F17/5068 , H01L21/31144 , H01L21/32139
摘要： A method of generating mask data, for a set of masks used to transfer a pattern for delineating a circuit pattern of a semiconductor integrated circuit, includes preparing design data having a design pattern corresponding to the pattern to be transferred on a semiconductor substrate; generating resized data by enlarging the design data by a resizing quantity; generating first mask data by filling a space area having a space width of a space quantity or less of the resized data; and generating second mask data, to be aligned with the first mask data, having a window portion for selectively exposing an area determined by enlarging the space area by the resizing quantity.
摘要翻译：一种用于生成用于传送用于描绘半导体集成电路的电路图案的图案的掩模组的掩模数据的方法，包括：准备具有与要在半导体衬底上传送的图案相对应的设计图案的设计数据; 通过调整大小的数量扩大设计数据来生成调整大小的数据; 通过填充具有空间大小的空间宽度的空间区域来生成第一掩模数据; 以及生成与所述第一掩模数据对准的第二掩模数据，所述第二掩模数据具有窗口部分，用于通过所述调整大小量选择性地暴露由所述空间区域扩大所确定的区域。

7. 发明授权

US07847363B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07847363B2
公开(公告)日：2010-12-07
申请号：US12370638
申请日：2009-02-13
申请人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
发明人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
IPC分类号： G11C5/00
CPC分类号： G11C5/063 , G11C16/0408 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
摘要翻译：用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。半导体存储器包括：多个有源区域AAi，AAi + 1，...，。。，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。。。沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。。。被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

8. 发明申请

US20100159709A1 MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：掩模图像校正方法，掩模图案检查方法，照相胶片制造方法和半导体器件制造方法
公开(公告)号：US20100159709A1
公开(公告)日：2010-06-24
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： H01L21/302 , G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

9. 发明授权

US07365018B2 Fabrication of semiconductor device for flash memory with increased select gate width 有权
标题翻译：具有增加选择栅极宽度的闪存半导体器件制造
公开(公告)号：US07365018B2
公开(公告)日：2008-04-29
申请号：US11319895
申请日：2005-12-28
申请人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
发明人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
IPC分类号： H01L21/302
CPC分类号： H01L21/28123 , H01L21/32139 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.
摘要翻译：使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以形成类似的最终结构。

10. 发明授权

US07120882B2 Method of setting process parameter and method of setting process parameter and/or design rule 有权
标题翻译：设置过程参数的方法和设置过程参数和/或设计规则的方法
公开(公告)号：US07120882B2
公开(公告)日：2006-10-10
申请号：US11105431
申请日：2005-04-14
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译：公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

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