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1. 发明授权

US06810369B1 Method for the computer-assisted production of a machine with geometrically-predetermined spherical components 有权
标题翻译：用于计算机辅助生产具有几何预定球形部件的机器的方法
公开(公告)号：US06810369B1
公开(公告)日：2004-10-26
申请号：US09720741
申请日：2000-12-29
申请人： Michael Ranold
发明人： Michael Ranold
IPC分类号： G06F760
CPC分类号： G06T17/00
摘要： The invention relates to a method for producing, in a computer-assisted way, a machine having pairs of geometrically-predetermined spherical components, i.e. a component B with recesses and a component W with bumps. According to said process, a spherical shell model is used to described mathematically the geometry of the vaulted surfaces formed by the recesses and the bumps of component W and component B.

2. 发明授权

US06782354B1 Method for producing simulation models and simulation system using simulation models 失效
标题翻译：使用仿真模型生成仿真模型和仿真系统的方法
公开(公告)号：US06782354B1
公开(公告)日：2004-08-24
申请号：US09686305
申请日：2000-10-11
申请人： Hiroyuki Ikegami
发明人： Hiroyuki Ikegami
IPC分类号： G06F760
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A simulation system includes a display, a model producing section and a first simulator. The model producing section produces a clock level simulation model and a first table from an algorithm description model and model interface data indicative of input and output of variables related to the algorithm description model. The clock level simulation model is used for simulating operations of resources in units of groups of allowable status transitions of the variables under constraint condition of the resources. The first table indicating correspondence relationship between the variables and the resources in units of status positions. The first simulator carries out the simulation of the algorithm description model to output variable values in each of the status positions.
摘要翻译：模拟系统包括显示器，模型产生部分和第一模拟器。模型生成部分从算法描述模型和表示与算法描述模型相关的变量的输入和输出的模型接口数据产生时钟级仿真模型和第一表。时钟级仿真模型用于在资源约束条件下模拟变量的允许状态转换组中资源的操作。第一个表显示变量与资源位置之间的对应关系。第一个模拟器执行算法描述模型的模拟，以在每个状态位置输出变量值。

3. 发明授权

US06725183B1 Method and apparatus for using DFSS to manage a research project 失效
公开(公告)号：US06725183B1
公开(公告)日：2004-04-20
申请号：US09387332
申请日：1999-08-31
申请人： James Norman Cawse
发明人： James Norman Cawse
IPC分类号： G06F760
CPC分类号： G06Q10/06 , B01J2219/00689 , B01J2219/00695 , B01J2219/007 , B01J2219/00745 , B01J2219/00747 , C40B30/08 , C40B40/18 , G06F17/50 , G06F2217/10
摘要： In an exemplary embodiment, an application of combinatorial materials development with minimum materials development, minimum variance, and maximum integration is provided. The embodiment is directed to a method of project development of a combinatorial materials development process using DFSS techniques having four major elements. The first element is the use of a design for six sigma (DFSS) process mapping to convert a complex and disorganized process structure to an organized structure that can be further analyzed. The second element comprises the use of quality function deployment houses as a method of flowing critical to quality characteristics (CTQ) through a research project. The third element comprises a transfer function that connects the overall steps of the project to the output which is measured as variability not as mean. Score cards are used as the “function” to total the variabilities of each process step. The final element comprises an extension of design of experiment (DOE) techniques.

4. 发明授权

US06401235B1 Method of and apparatus for producing exposure mask 失效
标题翻译：曝光掩模的制造方法和设备
公开(公告)号：US06401235B1
公开(公告)日：2002-06-04
申请号：US09082914
申请日：1998-05-21
申请人： Isao Ashida
发明人： Isao Ashida
IPC分类号： G06F760
CPC分类号： G03F1/78 , G03F1/68
摘要： The invention provides a method and an apparatus for producing an exposure mask by which an exposure mask can be produced in a reduced production period and with a high degree of reliability. Data division which does not have an influence on a pattern of an exposure mask is indicated, and indication data which include a predetermined index code is retrieved from layout data to produce a file. Then, the layout data are divided in accordance with the file, and for each of the divided layout data, a corresponding one of processes is selectively performed in accordance with a condition. EB files produced by such processes are unified in accordance with the file to produce a plotting job.
摘要翻译：本发明提供了一种用于制造曝光掩模的方法和装置，通过该方法和设备，可以在缩短的生产周期和高可靠性下产生曝光掩模。指示对曝光掩模的图案没有影响的数据划分，并且从布局数据中检索包括预定索引码的指示数据以产生文件。然后，根据文件划分布局数据，并且对于每个分割布局数据，根据条件选择性地执行相应的一个处理。通过这些过程产生的EB文件根据该文件统一以产生绘图作业。

5. 发明授权

US06370679B1 Data hierarchy layout correction and verification method and apparatus 有权
标题翻译：数据层次布局校正与验证方法及装置
公开(公告)号：US06370679B1
公开(公告)日：2002-04-09
申请号：US09154415
申请日：1998-09-16
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G06F760
CPC分类号： G03F1/36
摘要： A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.
摘要翻译：提供了用于校正维持原始布局的原始真实层级的光学邻近效应的集成电路布局的方法和装置。还提供了用于对光学邻近效应进行了校正的布局的设计规则检查的方法和装置。 OPC校正方法包括提供分级描述的集成电路布局作为第一输入和作为第二输入的特定的OPC校正标准集合。然后分析集成电路布局以识别满足所提供的OPC校正标准的布局的特征。在已经识别出需要校正的掩模上的区域之后，响应于特定的校正标准集而产生光学邻近校正数据。最后，生成将生成的光学邻近校正数据存储在与集成电路布局的层次结构对应的层次结构中的第一程序数据。由于输出校正数据以真实的分层格式保持，所以根据该方法校正OPC的布局能够通过传统的设计规则检查器进行处理，而不改变数据。

6. 发明授权

US06311143B1 Suiting apparatus and suiting method 失效
标题翻译：适合装置和方法
公开(公告)号：US06311143B1
公开(公告)日：2001-10-30
申请号：US09101203
申请日：1998-07-02
申请人： Masaharu Ishii
发明人： Masaharu Ishii
IPC分类号： G06F760
CPC分类号： G05B13/024
摘要： With respect to input data having the spread of errors or the like, “a suiting method” is to obtain a suiting function, which exist within a region of this spread, and which is highly robust. A suiting region (between an upper bound function M+(xi) and a lower bound function M−(xi)) is set based on the input data with the spread of errors. An inequality system is established with respect to the suiting region and the suiting function having undetermined parameters. A distance from a boundary of a solution region of the parameter values, corresponding to a boundary of the suiting region, is set, and a suiting function f(x) which has the parameter values maximizing the distance, is found. A broken line exhibits a suiting function f′(x) having low robustness, and a solid line exhibits a most-robust suiting function f(x) obtained from an application of this invention.
摘要翻译：对于具有误差扩散的输入数据等，“适用方法”是获得存在于该扩展区域内的适用函数，并且是高度鲁棒的。基于具有错误扩展的输入数据来设置适合区域（在上界函数M +（xi）和下界函数M-（xi）之间）。针对适合区域和具有不确定参数的诉讼函数建立了不平等系统。设定与参数值的解区域的边界对应于适合区域的边界的距离，找到具有最大化距离的参数值的自适应函数f（x）。虚线表示具有低鲁棒性的适合函数f'（x），并且实线表现出从本发明的应用获得的最强大的适合函数f（x）。

7. 发明授权

US06298473B1 Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device 失效
标题翻译：用于抑制图案失真以校正半导体器件中的图案数据的装置和方法
公开(公告)号：US06298473B1
公开(公告)日：2001-10-02
申请号：US09204281
申请日：1998-12-03
申请人： Yusaku Ono , Koichi Moriizumi
发明人： Yusaku Ono , Koichi Moriizumi
IPC分类号： G06F760
CPC分类号： G03F7/70441 , G03F1/36
摘要： A correction target edge extracting part of a layout pattern data correction apparatus extracts a correction target edge from circuit layout patterns. A density calculation region setting part of the apparatus sets density calculation regions around the center of the correction target edge. An area density calculating part calculates an area density of design patterns within the density calculation regions. Given the area density thus calculated, a correction pattern size calculating part calculates the size of a correction pattern to be superposed on the correction target edge. In accordance with the calculated size, a correction pattern generating part generates the correction pattern. A graphic calculating part adds up the correction pattern and design layout patterns to generate corrected layout patterns.
摘要翻译：布局图案数据校正装置的校正目标边缘提取部分从电路布局图案中提取校正目标边缘。设备的密度计算区域设置部分设置校正目标边缘的中心周围的密度计算区域。区域密度计算部分计算密度计算区域内的设计图案的面积密度。给定如此计算的面积密度，校正图案尺寸计算部分计算要校正对象边缘上叠加的校正图案的尺寸。根据计算出的尺寸，校正图案生成部生成校正图案。图形计算部分将校正图案和设计布局图案相加，以生成校正的布局图案。

8. 发明授权

US06278962B1 Hybrid linear-neural network process control 失效
公开(公告)号：US06278962B1
公开(公告)日：2001-08-21
申请号：US09165854
申请日：1998-10-02
申请人： Casimir C. Klimasauskas , John P. Guiver
发明人： Casimir C. Klimasauskas , John P. Guiver
IPC分类号： G06F760
CPC分类号： G05B19/042 , G05B13/027 , G05B13/0275
摘要： A hybrid analyzer having a data derived primary analyzer and an error correction analyzer connected in parallel is disclosed. The primary analyzer, preferably a data derived linear model such as a partial least squares model, is trained using training data to generate major predictions of defined output variables. The error correction analyzer, preferably a neural network model is trained to capture the residuals between the primary analyzer outputs and the target process variables. The residuals generated by the error correction analyzer is summed with the output of the primary analyzer to compensate for the error residuals of the primary analyzer to arrive at a more accurate overall model of the target process. Additionally, an adaptive filter can be applied to the output of the primary analyzer to further capture the process dynamics. The data derived hybrid analyzer provides a readily adaptable framework to build the process model without requiring up-front knowledge. Additionally, the primary analyzer, which incorporates the PLS model, is well accepted by process control engineers. Further, the hybrid analyzer also addresses the reliability of the process model output over the operating range since the primary analyzer can extrapolate data in a predictable way beyond the data used to train the model. Together, the primary and the error correction analyzers provide a more accurate hybrid process analyzer which mitigates the disadvantages, and enhances the advantages, of each modeling methodology when used alone.

9. 发明授权

US06243855B1 Mask data design method 有权
标题翻译：进行自动校正处理
公开(公告)号：US06243855B1
公开(公告)日：2001-06-05
申请号：US09161959
申请日：1998-09-29
申请人： Sachiko Kobayashi , Taiga Uno , Kazuko Yamamoto , Koji Hashimoto
发明人： Sachiko Kobayashi , Taiga Uno , Kazuko Yamamoto , Koji Hashimoto
IPC分类号： G06F760
CPC分类号： G03F7/70441 , G03F1/36
摘要： A correction target segment extracted from the design pattern is divided into lengths suited for correction. If the arrangement of the divided segments is a one-dimensional pattern, a correction value is obtained by conducting a one-dimensional process simulation to an arrangement within a predetermined distance from a divided segment in perpendicular direction. If the arrangement of the divided segments is a two-dimensional pattern, a correction value is obtained by two-dimensionally extracting a pattern included in a rectangular region having a predetermined distance from one point on the divided segment in perpendicular and horizontal directions and by conducting a two-dimensional process simulation to the extracted pattern.
摘要翻译：从设计图案提取的校正目标片段被划分为适合于校正的长度。如果分割段的排列是一维图案，则通过对垂直方向上的分割段的预定距离内的排列进行一维处理模拟来获得校正值。如果分割的片段的排列是二维图案，则通过二维地提取包括在具有预定距离的矩形区域中的图案，从而在垂直和水平方向上分割片段上的一个点，并且通过导线对提取的图案进行二维过程模拟。

10. 发明授权

US06801883B1 Code type control of caching parameters 有权
标题翻译：缓存参数的代码类型控制
公开(公告)号：US06801883B1
公开(公告)日：2004-10-05
申请号：US09585746
申请日：2000-06-02
申请人： Steven Hurlock
发明人： Steven Hurlock
IPC分类号： G06F760
CPC分类号： G06F12/121 , G06F12/0802
摘要： A code evaluation algorithm is used to determine optimal cache parameters. In evaluating the code, the algorithm uses a set of code characteristics the presence of which, or the degree of presence of which, impact the proper selection of cache parameters. Once the code characteristics have been selected, the algorithm uses boolean truth state tables or fuzzy logic membership set definitions to specify whether and when each code characteristic is true or false (i.e., present or absent) for a given set of code instructions. Programs are classified as having the following characteristics: 1) arithmetic intensive; 2) logic/decision intensive; 3) reference intensive; and/or 4) array/vector/table processing. To evaluate the code, the degree of presence or absence of these characteristics is described in logical fashion, using fuzzy logic. To logically evaluate and relate such “fuzzy” concepts, the algorithm uses fuzzy logic membership functions to determine the degree to which there exist a small number, medium number or large number of instances of a particular class of operator in the code analyzed. Next, the algorithm defines a fuzzy logic rule base which relates (e.g., by implication) the presence or absence (i.e., truth or falsehood) of the condition impacting proper selection of cache parameters to conclusions regarding the selection of cache parameters. The algorithm then determines (evaluates) the conclusions regarding the proper selection of cache parameters by evaluating the conditions impacting the conclusions while applying the rule base rules. In particular, the algorithm uses the “Mandani Product” inference engine for computational simplicity. The center of gravity of the fuzzy outcomes is computed and the result is discretized yielding a crisp, meaningful result representing an optimal cache parameter choice.
摘要翻译：代码评估算法用于确定最优缓存参数。在评估代码时，算法使用一组代码特征，其中存在或存在程度影响缓存参数的正确选择。一旦选择了代码特征，该算法使用布尔真值状态表或模糊逻辑成员关系集定义来指定对于给定的一组代码指令，每个代码特性是否以及每个代码特性是真还是假（即存在或不存在）。程序分为以下特点：1）算术密集型; 2）逻辑/决策密集; 3）参考密集; 和/或4）数组/向量/表处理。为了评估代码，使用模糊逻辑以逻辑方式描述这些特征的存在或不存在程度。为了逻辑地评估和关联这种“模糊”概念，该算法使用模糊逻辑隶属函数来确定在分析的代码中存在特定类别的算子的小数量，中等数量或大数量的实例的程度。接下来，该算法定义了一个模糊逻辑规则库，其涉及（例如通过暗示）影响高速缓存参数的适当选择的条件的存在或不存在（即，真实或虚假）与关于高速缓存参数的选择的结论。然后，该算法通过在应用规则库规则时评估影响结论的条件来确定（评估）关于缓存参数的适当选择的结论。特别地，该算法使用“Mandani Product”推理机来简化计算。计算模糊结果的重心，并将结果离散化，产生表示最佳缓存参数选择的清晰有意义的结果。

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