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1. 发明授权

US5539333A CMOS receiver circuit 失效
标题翻译： CMOS接收电路
公开(公告)号：US5539333A
公开(公告)日：1996-07-23
申请号：US376705
申请日：1995-01-23
申请人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
发明人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
IPC分类号： G06F1/10 , H03K19/0185 , H03K19/094 , H04L25/02
CPC分类号： H04L25/0292 , G06F1/10 , H03K19/018528 , H03K19/09429 , H04L25/0272 , H04L25/0276 , H04L25/028
摘要： A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.
摘要翻译：用于数据处理系统的时钟分配系统在CMOS技术中实现，其中全摆幅差分时钟信号由驱动器电路转换为低电压摆幅差分时钟信号，然后在每个时钟信号返回到全频差分时钟信号接收电路。

2. 发明授权

US5525914A CMOS driver circuit 失效
标题翻译： CMOS驱动电路
公开(公告)号：US5525914A
公开(公告)日：1996-06-11
申请号：US376704
申请日：1995-01-23
申请人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
发明人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
IPC分类号： H03K3/356 , H03K19/0185
CPC分类号： H03K3/35613 , H03K3/356034
摘要： A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.
摘要翻译：用于数据处理系统的时钟分配系统在CMOS技术中实现，其中全摆幅差分时钟信号由驱动器电路转换为低电压摆幅差分时钟信号，然后在每个时钟信号返回到全频差分时钟信号接收电路。

3. 发明授权

US4567561A Large scale integration data processor signal transfer mechanism 失效
标题翻译：大规模集成数据处理器信号传递机制
公开(公告)号：US4567561A
公开(公告)日：1986-01-28
申请号：US334185
申请日：1981-12-24
申请人： Virgil D. Wyatt , Wayne R. Kraft , Nandor G. Thoma
发明人： Virgil D. Wyatt , Wayne R. Kraft , Nandor G. Thoma
IPC分类号： G06F7/00 , G06F9/30 , G06F13/40 , G06F15/78 , G06F9/00
CPC分类号： G06F13/4077 , G06F15/7864 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus. The signal transfer mechanism further includes processor control circuitry coupled to the signal source and signal destination circuitry for enabling the signal source circuitry to put a plural-bit data signal onto the data bus during a first processor control cycle and for enabling the signal destination circuitry to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.
摘要翻译：提供数字数据信号传送机制，用于形成在集成电路芯片上的大规模集成数字数据处理器电路。信号传送机构包括形成在集成电路芯片上用于在芯片上的不同位置之间传送多位二进制数据信号的多位数据总线。信号传送机构还包括形成在集成电路芯片上并耦合到多位数据总线的多位信号源电路和多位信号目的地电路，用于分别向多位数据信号提供多位数据信号并接收多位数据信号从公共汽车。信号传送机构还包括耦合到信号源和信号目的地电路的处理器控制电路，用于使信号源电路在第一处理器控制周期期间将多位数据信号放入数据总线上，并使信号目的地电路能够在第二和不同的处理器控制周期期间从总线接收该多位数据信号。多位数据总线的固有电容用于在第一和第二和任何中间处理器控制周期期间存储多位数据信号。

4. 发明授权

US4484268A Apparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arrays 失效
标题翻译：使用多个可复用可编程逻辑阵列对操作码进行解码的装置和方法
公开(公告)号：US4484268A
公开(公告)日：1984-11-20
申请号：US350661
申请日：1982-02-22
申请人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
发明人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30 , H03K19/177 , G06F9/00
CPC分类号： G06F9/267
摘要： A plurality of programmable logic arrays (PLA's) operate in parallel, each to decode an operation code (OP code). A portion of the OP code is decoded to select one of the PLA's, and the decoded OP code from the selected PLA is gated through a multiplexer to provide the control code corresponding to the OP code.
摘要翻译：多个可编程逻辑阵列（PLA）并行操作，每个解码操作码（OP代码）。对OP代码的一部分进行解码以选择PLA中的一个，并且通过多路复用器选择来自所选择的PLA的解码的OP代码以提供对应于OP代码的控制代码。

5. 发明授权

US5619158A Hierarchical clocking system using adaptive feedback 失效
标题翻译：使用自适应反馈的分层计时系统
公开(公告)号：US5619158A
公开(公告)日：1997-04-08
申请号：US516704
申请日：1995-08-18
申请人： Humberto F. Casal , Joel R. Davidson , Hehching H. Li , Yuan C. Lo , Trong D. Nguyen , Campbell H. Snyder , Nandor G. Thoma
发明人： Humberto F. Casal , Joel R. Davidson , Hehching H. Li , Yuan C. Lo , Trong D. Nguyen , Campbell H. Snyder , Nandor G. Thoma
IPC分类号： G06F1/10 , H03K5/13
CPC分类号： G06F1/10
摘要： A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.
摘要翻译：以分层方式创建用于复杂电子设备的时钟系统，由此主时钟脉冲被提供给多个数字脉冲对准器，这些数字脉冲对准器又将现场可更换单元级的相位对准时钟信号提供给从时钟或数字相位对准器在现场可更换单元级别的从时钟或数字相位对准器又向相应芯片上的定时节点提供对准的时钟脉冲。层次结构的第三级向系统芯片上的各个使用电路提供类似的对齐脉冲。数字相位对准器将下一级的定时节点处的输出脉冲与在每个电平处提供给数字相位对准器的参考脉冲对准，确保到达利用电路的定时脉冲与时钟脉冲同步地对准主时钟。该系统显着简化了现场可更换单元中现场可更换单元或单个组件的更换。该系统是自相位和自校正，以适应由于各级定时延迟的任何变化引起的定时未对准，从而减少必须适应的抖动。

6. 发明授权

US4488067A Tristate driver circuit with low standby power consumption 失效
标题翻译：三态驱动电路具有低待机功耗
公开(公告)号：US4488067A
公开(公告)日：1984-12-11
申请号：US533392
申请日：1983-09-19
申请人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/20 , H03K19/017
CPC分类号： H03K19/09429
摘要： Improved tristate control circuitry is provided for a driver circuit formed on an integrated circuit chip. A parallel-connected combination of a depletion mode transistor and an enhancement mode transistor is connected in series in the voltage supply path for the driver circuit for controlling whether the driver circuit is in an active mode or a standby mode by controlling the supplying of operating voltage thereto. A further enhancement mode transistor provides a shunting action between the driver circuit side of the parallel-connected transistors and circuit ground to further aid in the control of the driver circuit operating mode.
摘要翻译：为在集成电路芯片上形成的驱动电路提供改进的三态控制电路。耗尽型晶体管和增强型晶体管的并联组合串联连接在用于驱动电路的电压供给路径中，用于通过控制提供工作电压来控制驱动电路是处于活动模式还是待机模式到此。另外的增强模式晶体管在并联晶体管的驱动器电路侧和电路接地之间提供分流动作，以进一步有助于控制驱动器电路工作模式。

7. 发明授权

US06642802B2 Ring oscillator providing single event transient immunity 失效
公开(公告)号：US06642802B2
公开(公告)日：2003-11-04
申请号：US10029716
申请日：2001-12-20
申请人： Kenneth R. Knowles , Nandor G. Thoma
发明人： Kenneth R. Knowles , Nandor G. Thoma
IPC分类号： H03B2700
CPC分类号： H03K3/013 , H03K3/0315
摘要： A dual path ring oscillator core includes three dual path inverters, each having a first inverter and a second inverter. Within the first inverter, one transistor is coupled to a first output of a previous dual path inverter, while another transistor is coupled to a second output of the previous dual path inverter. Within the second inverter, one transistor is coupled to the second output of the previous dual path inverter, while another transistor is coupled to the previous dual path inverter's first output. A first and a final dual path inverter are analogously coupled. A transient pulse will not propagate through successive dual path inverter stages. A dual to single path converter is coupled to receive signals output by the final dual path inverter. If a transient signal appears at a dual to single path converter input, stray output node capacitance maintains a correct output signal value.

8. 发明授权

US4583193A Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus 失效
标题翻译：用于将多个可编程逻辑阵列耦合到公共总线的集成电路机制
公开(公告)号：US4583193A
公开(公告)日：1986-04-15
申请号：US350681
申请日：1982-02-22
申请人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
发明人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
IPC分类号： H01L21/822 , G06F9/22 , G06F9/26 , G06F9/28 , H01L21/82 , H01L27/04 , H03K19/173 , H03K19/177 , G06F13/38
CPC分类号： G06F9/28 , G06F9/223 , G06F9/267
摘要： An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines. The buffer stages for each programmable logic array are responsive to the strobe signal for its programmable logic array for discharging during the second time interval those bus lines for which its programmable logic array output lines are at a particular binary value.
摘要翻译：提供了一种集成电路机制，用于将分离的输出线组从多个可编程逻辑阵列耦合到多行信号传输总线的同一组总线。该耦合机构包括用于在第一时间间隔期间预充电每个总线的预充电电路。该耦合机构还包括用于每个可编程逻辑阵列的单独选通信号线和用于在用于选择特定可编程逻辑阵列的第二时间间隔期间激活选通信号线之一的电路。该耦合机构还包括用于每个可编程逻辑阵列的单独的输出缓冲器。每个这样的输出缓冲器包括用于将不同的可编程逻辑阵列输出线分别耦合到它们各自的总线的多个缓冲级。每个可编程逻辑阵列的缓冲级响应于其可编程逻辑阵列的选通信号，用于在第二时间间隔期间对其可编程逻辑阵列输出线处于特定二进制值的总线进行放电。

9. 发明授权

US4500800A Logic performing cell for use in array structures 失效
标题翻译：用于阵列结构的逻辑执行单元
公开(公告)号：US4500800A
公开(公告)日：1985-02-19
申请号：US413043
申请日：1982-08-30
申请人： Moises Cases , Wayne R. Kraft , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Moises Cases , Wayne R. Kraft , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/096 , H03K19/177 , H03K19/017 , H03K17/16
CPC分类号： H03K19/1772 , H03K19/096
摘要： As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.
摘要翻译：作为对先前已知的PLA（编程逻辑阵列）结构的具体改进，由串联链式电荷转移电路中的FET器件形成，目前公开的“修改”PLA结构包括以下组合：（a）电平移位电路，集成到位已知结构的分级级，用于减小这些级的输出中的电压摆幅，从而减少到后续阵列级的寄生耦合，并减少后级的运行延迟; （b）在已知结构的OR阵列阶段的输出端处添加的离散电容，用于在该级的读出（验证时钟）之前维持和加强在该级中累积的充电条件; 以及（c）与所述经修改的结构的阶段耦合的时间相关时钟功能源，选择所述定时关系以便减少整个结构的运行延迟，同时提高其操作的完整性。

10. 发明授权

US06487134B2 Single-event upset tolerant latch for sense amplifiers 有权
标题翻译：用于读出放大器的单事件不耐受锁存器
公开(公告)号：US06487134B2
公开(公告)日：2002-11-26
申请号：US09927059
申请日：2001-08-09
申请人： Nandor G. Thoma , Scott E. Doyle
发明人： Nandor G. Thoma , Scott E. Doyle
IPC分类号： G11C700
CPC分类号： G11C7/06
摘要： A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.
摘要翻译：公开了一种用于读出放大器的单事件容错读出锁存电路。单事件歪曲容忍检测锁存电路包括第一组隔离晶体管，第二组隔离晶体管，第一组双通道反相器，第二组双通道反相器和隔离晶体管。第一组隔离晶体管耦合到第一位线，第二组隔离晶体管耦合到第二位线。第二个位线是第一个位线的补充。第一组双通道逆变器耦合到第一组隔离晶体管，并且第一组双通道反相器包括连接到与串联连接到第四晶体管的第三晶体管串联的第二晶体管的第一晶体管。第二组双通道逆变器耦合到第二组隔离晶体管，第二组双通道反相器包括连接到与串联连接到第八晶体管的第七晶体管串联连接的第六晶体管的第五晶体管。隔离晶体管将第一组和第二组双通道逆变器耦合到地。

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