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1. 发明申请

US20050251359A1 METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR HIGH SPEED MEMORY TESTING 失效
标题翻译：用于高速记忆测试的方法，装置和计算机程序产品
公开(公告)号：US20050251359A1
公开(公告)日：2005-11-10
申请号：US10840559
申请日：2004-05-06
申请人： Tai Cao , Khanh Nguyen , Aquilur Rahman
发明人： Tai Cao , Khanh Nguyen , Aquilur Rahman
IPC分类号： G06F19/00
CPC分类号： G06F11/263 , G06F11/273
摘要： For testing a device under test (“DUT”) a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.
摘要翻译：为了测试被测设备（“DUT”），测试规范在计算机系统中通过引脚向量生成器进程进行转换，其中包括生成测试向量。 DUT具有许多输入引脚，并且这样的引脚矢量用于信号来驱动一个这样的引脚。引脚向量被压缩并保存。在测试初始化时，引导向量的载入被加载到具有一系列存储器级并且从计算机系统延伸到测试头中的通道卡的管道中。流水线在数据传输周期中运行，每个周期提供W位。在解压缩器读取周期中，引脚向量在相应的通道卡处被解压缩。每个解压缩器周期读取X位，W大于X，使得流水线可以比解压缩器执行其读周期更不频繁地执行其数据传送周期。

2. 发明授权

US06337884B1 Circuitry for allowing two drivers to communicate with two receivers using one transmission line 失效
标题翻译：允许两个驱动器使用一条传输线与两个接收机通信的电路
公开(公告)号：US06337884B1
公开(公告)日：2002-01-08
申请号：US09096502
申请日：1998-06-12
申请人： Tai Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
发明人： Tai Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
IPC分类号： H04B300
CPC分类号： H04L25/0292 , G06F13/4072 , H04L5/04 , H04L25/028
摘要： The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.
摘要翻译：本发明允许将两个数字信号从一个集成电路同时传输到另一个集成电路。两个数字信号利用分压电路进行编码，然后由一个传输线传输到第二集成电路芯片。第二集成电路芯片解码第一数字信号，然后利用该解码的数字信号进一步解码第二数字信号。

3. 发明授权

US5663663A Mixed voltage interface converter 失效
标题翻译：混合电压接口转换器
公开(公告)号：US5663663A
公开(公告)日：1997-09-02
申请号：US638028
申请日：1996-04-26
申请人： Tai Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
发明人： Tai Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018521 , H03K19/018514
摘要： The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.
摘要翻译：本发明有助于来自使用第一CMOS技术实现的信号的信号的通信，该第一CMOS技术需要用于操作的第一电压电平供给用第二CMOS技术实现的电路，该第二CMOS技术需要用于操作的第二电压电平供应，其中第一和第二电压电平供应不是等于。本发明从由第一CMOS技术实现的电路接收具有第一电压电平的信号，该第一电压电平对于用第二CMOS技术实现的电路的输入是不可接受的。该信号被转换为对于用第二CMOS技术实现的电路的输入可接受的第二电压电平，然后被传送到用第二CMOS技术实现的电路，该第二CMOS技术需要用于操作的第二电压电平。

4. 发明申请

US20050091262A1 Method, apparatus, and program for finding and navigating to items in a set of web pages 审中-公开
标题翻译：用于查找和导航到一组网页中的项目的方法，装置和程序
公开(公告)号：US20050091262A1
公开(公告)日：2005-04-28
申请号：US10988079
申请日：2004-11-12
申请人： Tai Cao
发明人： Tai Cao
IPC分类号： G06F17/30 , G06F7/00
CPC分类号： G06F16/9535
摘要： A mechanism is provided for highlighting items of interest in a set of web pages. The link highlighting mechanism may retrieve and examine web pages referenced by the instant web page. In this manner, the link highlighting mechanism may crawl through a set of web pages and highlight links that direct the user to the item of interest. The link highlighting mechanism may also record a user's click sequence to determine the most recently or most frequently visited links. The mechanism may then highlight the most recently or most frequently visited links to allow easy and quick navigation to items that are of particular interest to the user. The user may also enter properties of an item of interest, such as a file type or link type. The link highlighting mechanism examines a web page for items and links that match the property. If the user is using a mobile computing device or is otherwise operating with limited bandwidth, the highlighting mechanism may reside on a server. Thus, the server may transmit only the item of interest unless otherwise instructed by the user.
摘要翻译：提供了一种用于突出显示一组网页中的兴趣项的机制。链接突出显示机制可以检索和检查由即时网页引用的网页。以这种方式，链接突出显示机制可以爬过一组网页并突出显示将用户引导到感兴趣的项目的链接。链接突出显示机制还可以记录用户的点击序列以确定最近或最常访问的链接。该机制然后可以突出显示最近或最常访问的链接，以便容易且快速地导航到用户特别感兴趣的项目。用户还可以输入感兴趣的项目的属性，诸如文件类型或链接类型。链接突出显示机制检查与属性匹配的项目和链接的网页。如果用户正在使用移动计算设备或以其他方式以有限的带宽进行操作，则高亮机制可以驻留在服务器上。因此，除非用户另有指示，服务器可以仅发送感兴趣的项目。

5. 发明授权

US5525914A CMOS driver circuit 失效
标题翻译： CMOS驱动电路
公开(公告)号：US5525914A
公开(公告)日：1996-06-11
申请号：US376704
申请日：1995-01-23
申请人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
发明人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
IPC分类号： H03K3/356 , H03K19/0185
CPC分类号： H03K3/35613 , H03K3/356034
摘要： A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.
摘要翻译：用于数据处理系统的时钟分配系统在CMOS技术中实现，其中全摆幅差分时钟信号由驱动器电路转换为低电压摆幅差分时钟信号，然后在每个时钟信号返回到全频差分时钟信号接收电路。

6. 发明申请

US20050083774A1 METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A MEMORY ARRAY WITH DYNAMIC WORD LINE DRIVER/DECODERS 失效
标题翻译：用动态字线驱动器/解码器在存储器阵列中降低功耗的方法和装置
公开(公告)号：US20050083774A1
公开(公告)日：2005-04-21
申请号：US10687238
申请日：2003-10-16
申请人： Tai Cao , Sam Chu , Joseph McGill , Michael Vaden
发明人： Tai Cao , Sam Chu , Joseph McGill , Michael Vaden
IPC分类号： G11C7/10 , G11C7/22 , G11C8/08 , G11C8/18 , G11C8/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/22 , G11C7/225 , G11C8/08 , G11C8/18
摘要： A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.
摘要翻译：存储器阵列包括存储单元，其具有多个部分和解码器，所述部分和解码器耦合到相应的部分，用于对N位地址信号进行解码，并响应地确定由地址信号选择的一条字线上的信号。本地时钟缓冲器耦合到解码器中的相应解码器，用于接收时钟信号和包括N位地址信号的M个最高有效位的地址信号并产生相应的定时信号。解码器从其各自的本地时钟缓冲器接收定时信号。每个解码器可操作以响应于定时信号的相位交替地预充电和评估N位地址信号。每个本地时钟缓冲器可操作地响应于地址信号的M位的状态，用于在保持其定时信号处于无效状态并使其定时信号跟随时钟信号之间进行选择。

7. 发明授权

US5864584A Circuitry for allowing two drivers to communicate with two receivers using one transmission line 失效
公开(公告)号：US5864584A
公开(公告)日：1999-01-26
申请号：US387518
申请日：1995-02-13
申请人： Tai Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
发明人： Tai Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
IPC分类号： G06F13/40 , H04L5/04 , H04L25/02 , H04J15/00 , H04B14/06 , H04L25/34
CPC分类号： H04L25/0292 , G06F13/4072 , H04L25/028 , H04L5/04
摘要： The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

8. 发明授权

US5541534A Mixed voltage interface converter 失效
标题翻译：混合电压接口转换器
公开(公告)号：US5541534A
公开(公告)日：1996-07-30
申请号：US387517
申请日：1995-02-13
申请人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Thanh D. Trinh , Lloyd A. Walls
发明人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Thanh D. Trinh , Lloyd A. Walls
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018521 , H03K19/018514
摘要： The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.
摘要翻译：本发明有助于来自使用第一CMOS技术实现的信号的信号的通信，该第一CMOS技术需要用于操作的第一电压电平供应到用第二CMOS技术实现的电路，该第二CMOS技术需要用于操作的第二电压电平供应，其中第一和第二电压电平供应不是等于。本发明从由第一CMOS技术实现的电路接收具有第一电压电平的信号，该第一电压电平对于用第二CMOS技术实现的电路的输入是不可接受的。该信号被转换为对于用第二CMOS技术实现的电路的输入可接受的第二电压电平，然后被传送到用第二CMOS技术实现的电路，该第二CMOS技术需要用于操作的第二电压电平。

9. 发明授权

US5539333A CMOS receiver circuit 失效
标题翻译： CMOS接收电路
公开(公告)号：US5539333A
公开(公告)日：1996-07-23
申请号：US376705
申请日：1995-01-23
申请人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
发明人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
IPC分类号： G06F1/10 , H03K19/0185 , H03K19/094 , H04L25/02
CPC分类号： H04L25/0292 , G06F1/10 , H03K19/018528 , H03K19/09429 , H04L25/0272 , H04L25/0276 , H04L25/028
摘要： A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.
摘要翻译：用于数据处理系统的时钟分配系统在CMOS技术中实现，其中全摆幅差分时钟信号由驱动器电路转换为低电压摆幅差分时钟信号，然后在每个时钟信号返回到全频差分时钟信号接收电路。

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