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1. 发明授权

US6008123A Method for using a hardmask to form an opening in a semiconductor substrate 失效
标题翻译：使用硬掩模在半导体衬底中形成开口的方法
公开(公告)号：US6008123A
公开(公告)日：1999-12-28
申请号：US963687
申请日：1997-11-04
申请人： Taeho Kook , Alvaro Maury , Kurt G. Steiner , Tungsheng Yang
发明人： Taeho Kook , Alvaro Maury , Kurt G. Steiner , Tungsheng Yang
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/768 , H01L29/78 , H01L21/8242
CPC分类号： H01L21/31144 , H01L21/76816 , Y10S438/947
摘要： The present invention provides a method of forming a opening in a semiconductor dielectric layer. In an advantageous embodiment, the method comprises the steps of forming a hardmask layer on the dielectric layer wherein the hardmask layer has an etch rate less than an etch rate of the dielectric layer, forming a guide opening through the hardmask layer, forming a spacer within the guide opening that reduces a diameter of the guide opening and forming the opening in the dielectric layer through the guide opening. The method may further include the steps of depositing a conductive material in the opening and guide opening and over at least a portion of the hardmask layer that extends beyond the guide opening, and removing the hardmask layer and the conductive material layer that extend beyond the guide opening. In certain embodiments, the contact opening may be formed to a width equal to or less than 0.25 .mu.m.
摘要翻译：本发明提供一种在半导体电介质层中形成开口的方法。在有利的实施例中，该方法包括以下步骤：在电介质层上形成硬掩模层，其中硬掩模层的蚀刻速率小于电介质层的蚀刻速率，形成通过硬掩模层的引导开口，所述引导开口减小所述引导开口的直径并且通过所述引导开口在所述介电层中形成所述开口。该方法可以进一步包括以下步骤：将导电材料沉积在开口和引导开口中以及在延伸超过引导开口的硬掩模层的至少一部分之上，以及移除延伸超过引导件的硬掩模层和导电材料层开放在某些实施例中，接触开口可以形成为等于或小于0.25μm的宽度。

2. 发明授权

US08872311B2 Semiconductor device and a method of manufacture therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08872311B2
公开(公告)日：2014-10-28
申请号：US10778453
申请日：2004-02-13
申请人： Nace Rossi , Alvaro Maury
发明人： Nace Rossi , Alvaro Maury
IPC分类号： H01L23/58 , H01L21/768 , H01L21/8238 , H01L29/66
CPC分类号： H01L21/76831 , H01L21/76832 , H01L21/76895 , H01L21/76897 , H01L21/823871 , H01L29/6659
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, in one particularly advantageous embodiment, includes a multi layer etch stop located over a substrate, wherein the multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer. Located over the multi layer etch stop is a dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop. A conductive plug is typically located within the opening, wherein an insulative spacer is located between the conductive plug and the second silicon-rich nitride layer.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。在一个特别有利的实施例中，半导体器件包括位于衬底上的多层蚀刻停止件，其中多层蚀刻停止件具有位于第一绝缘层上方的第一绝缘层和第二富硅氮化物层。位于多层蚀刻停止点上方的是具有形成在其中的开口的电介质层，其延伸穿过多层蚀刻停止件的至少一部分。导电插塞通常位于开口内，其中绝缘垫片位于导电插塞和第二富硅氮化物层之间。

3. 发明授权

US07163438B2 Zone polishing using variable slurry solid content 有权
标题翻译：使用可变浆料固体含量进行区域抛光
公开(公告)号：US07163438B2
公开(公告)日：2007-01-16
申请号：US11208829
申请日：2005-08-22
申请人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
发明人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
IPC分类号： B24B49/00 , B24B7/00 , B24B1/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
摘要翻译：一种用于与化学机械抛光工具一起用于平坦化具有不规则拓扑的半导体衬底的浆料分配装置。该设备包括具有悬挂在抛光垫上的第一端的浆料分配歧管和用于安装到化学机械抛光工具的第二端。浆料分配歧管具有位于悬浮歧管下方的线性阵列的喷嘴。每个喷嘴提供从分叉供应管线供应的经调节的浆料混合物。供应浆料的第一分支和供应去离子水的第二分支。根据其表面拓扑结构，每个喷嘴能够提供特定的浆料浓度以降低或提高基材上特定区带区域的抛光速率。

4. 发明授权

US06910907B2 Contact for use in an integrated circuit and a method of manufacture therefor 失效
标题翻译：用于集成电路的接触及其制造方法
公开(公告)号：US06910907B2
公开(公告)日：2005-06-28
申请号：US10716299
申请日：2003-11-18
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L21/768 , H01R13/28 , H01R25/00
CPC分类号： H01L21/76877
摘要： The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.
摘要翻译：本发明提供了一种用于集成电路的接点及其制造方法，以及包括上述接触的集成电路。根据本发明的原理的触点可以包括位于基板中的通孔和位于通孔中的接触塞，其中接触插塞具有从其中移除的凹口的第一部分和填充该通孔的第二部分缺口。

5. 发明授权

US06372605B1 Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing 有权
标题翻译：附加蚀刻以减少半导体处理中浅沟槽隔离的抛光时间
公开(公告)号：US06372605B1
公开(公告)日：2002-04-16
申请号：US09603340
申请日：2000-06-26
申请人： Stephen C. Kuehne , Alvaro Maury , Scott F. Shive
发明人： Stephen C. Kuehne , Alvaro Maury , Scott F. Shive
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In one implementation wet-etching and/or sputter etch-back (SEB) is performed prior to applying a reverse-tone mask. In another implementation a wet etching step is performed after the reverse-tone mask is stripped. One significant result of each of these steps is a reduction in the height and width of at least some of the oxide horns that remain after the reverse-tone mask is stripped. As such, the oxide structures that need to be planarized during CMP will be smaller than those of the prior art. Moreover, since the resulting oxide structures that need to be planarized by CMP processing are smaller, the oxide layer can be initially applied at a smaller thickness than that of the prior art. As such, the duration of CMP processing can be correspondingly shorter, resulting in polished semiconductor wafer surfaces with greater uniformity than that provided by the prior art.
摘要翻译：在半导体处理期间形成浅沟槽隔离（STI）结构期间，在化学机械处理之前执行附加的氧化物还原蚀刻步骤。在一个实施方式中，在应用反向色调掩模之前执行湿蚀刻和/或溅射蚀回（SEB）。在另一实施方案中，在剥离反色调掩模之后执行湿蚀刻步骤。这些步骤中的每一个的一个显着结果是减少在消除反色调掩模之后残留的至少一些氧化物喇叭的高度和宽度。因此，在CMP期间需要平坦化的氧化物结构将小于现有技术的氧化物结构。此外，由于需要通过CMP处理进行平坦化的所得到的氧化物结构较小，所以可以以比现有技术更薄的厚度开始施加氧化物层。因此，CMP处理的持续时间可以相应地更短，导致抛光的半导体晶片表面具有比现有技术提供的更大的均匀性。

6. 发明授权

US6110831A Method of mechanical polishing 失效
标题翻译：机械抛光方法
公开(公告)号：US6110831A
公开(公告)日：2000-08-29
申请号：US923316
申请日：1997-09-04
申请人： James Thomas Cargo , Ronald James Alexander Holmes , Ruichen Liu , Alvaro Maury
发明人： James Thomas Cargo , Ronald James Alexander Holmes , Ruichen Liu , Alvaro Maury
IPC分类号： H01L21/3205 , H01L21/304 , H01L21/3105 , H01L21/66 , H01L23/544 , H01L21/465
CPC分类号： B24B37/013 , H01L21/31053 , H01L22/26 , H01L22/34 , H01L2924/0002
摘要： A method of manufacturing integrated circuits utilizing chemical mechanical polishing (CMP) is disclosed. A dielectric layer, illustratively, having a dopant, dye, etc. termed a "marker layer" is formed upon a wafer having partially fabricated integrated circuits thereon. An undoped, undyed layer is deposited upon the marker layer. The undoped or undyed layer is polished and the waste slurry is monitored until a signal indicating the exposure of the signal layer is obtained. Analysis of the signal provides an indication of when the CMP process should be terminated.
摘要翻译：公开了利用化学机械抛光（CMP）制造集成电路的方法。示例性地，具有称为“标记层”的掺杂剂，染料等的介电层形成在其上具有部分制造的集成电路的晶片上。未标记的未染色层沉积在标记层上。对未掺杂或未染色的层进行抛光，并监测废料浆料，直到获得指示信号层曝光的信号。信号分析提供了CMP过程何时终止的指示。

7. 发明授权

US06033293A Apparatus for performing chemical-mechanical polishing 失效
标题翻译：用于进行化学机械抛光的装置
公开(公告)号：US06033293A
公开(公告)日：2000-03-07
申请号：US947178
申请日：1997-10-08
申请人： Annette Margaret Crevasse , Alvaro Maury , Sanjay Patel , John Thomas Sowell
发明人： Annette Margaret Crevasse , Alvaro Maury , Sanjay Patel , John Thomas Sowell
IPC分类号： B24B37/11 , B24B45/00 , B24D9/10
CPC分类号： B24B37/11 , B24B45/00
摘要： An apparatus and method for performing chemical-mechanical polishing is disclosed in which the pad is secured to the platen without the use of adhesives. A polishing pad and a platen are secured together by a releasable attractive force; the force may comprise a vacuum or electromagnetic force, and the pad has a hard or magnetic backside layer for facing the plating and responding to the attractive force. This invention has particular application to chemical-mechanical polishing for use in planarizing dielectrics.
摘要翻译：公开了一种用于进行化学机械抛光的装置和方法，其中垫不用粘合剂固定在压板上。抛光垫和压板通过可释放的吸引力固定在一起; 力可以包括真空或电磁力，并且垫具有用于面对镀层并响应于吸引力的硬或磁性背面层。本发明特别适用于平面化电介质中使用的化学机械抛光。

8. 发明申请

US20090108359A1 A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREFOR 审中-公开
标题翻译：一种半导体器件及其制造方法
公开(公告)号：US20090108359A1
公开(公告)日：2009-04-30
申请号：US11930728
申请日：2007-10-31
申请人： Nace Rossi , Alvaro Maury
发明人： Nace Rossi , Alvaro Maury
IPC分类号： H01L27/105 , H01L29/78
CPC分类号： H01L21/76832 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.
摘要翻译：本发明提供一种半导体器件和包括该半导体器件的集成电路。在一个实施例中，半导体器件包括：（1）位于衬底上方的栅极结构，所述栅极结构包括栅极电介质和栅电极; （2）位于靠近栅极结构的衬底内的源极/漏极区域，（3）位于衬底上方的多层蚀刻停止器，其中该蚀刻停止件具有第一绝缘层和位于第一衬底上方的第二富硅氮化物层绝缘层，（4）位于所述蚀刻停止点上方的电介质层，所述电介质层具有形成在其中的开口，所述开口延伸穿过所述多层蚀刻停止件的至少一部分，（5）位于所述开口内并电接触的导电插塞栅电极和源极/漏极区之一，以及（6）位于导电插塞和第二富硅氮化物层之间的绝缘间隔物。

9. 发明申请

US20080079083A1 Semiconductor device and a method of manufacture therefor 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080079083A1
公开(公告)日：2008-04-03
申请号：US11930794
申请日：2007-10-31
申请人： Nace Rossi , Alvaro Maury
发明人： Nace Rossi , Alvaro Maury
IPC分类号： H01L29/78
CPC分类号： H01L21/76831 , H01L21/76832 , H01L21/76895 , H01L21/76897 , H01L21/823871 , H01L29/6659
摘要： The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.
摘要翻译：本发明提供一种半导体器件和包括该半导体器件的集成电路。在一个实施例中，半导体器件包括：（1）位于衬底上方的栅极结构，所述栅极结构包括栅极电介质和栅电极; （2）位于靠近栅极结构的衬底内的源极/漏极区域，（3）位于衬底上方的多层蚀刻停止器，其中该蚀刻停止件具有第一绝缘层和位于第一衬底上方的第二富硅氮化物层绝缘层，（4）位于所述蚀刻停止点上方的电介质层，所述电介质层具有形成在其中的开口，所述开口延伸穿过所述多层蚀刻停止件的至少一部分，（5）位于所述开口内并电接触的导电插塞栅电极和源极/漏极区之一，以及（6）位于导电插塞和第二富硅氮化物层之间的绝缘间隔物。

10. 发明申请

US20050179116A1 Semiconductor device and a method of manufacture therefor 有权
公开(公告)号：US20050179116A1
公开(公告)日：2005-08-18
申请号：US10778454
申请日：2004-02-13
申请人： Nace Rossi , Alvaro Maury
发明人： Nace Rossi , Alvaro Maury
IPC分类号： C23C16/40 , H01L21/302 , H01L21/316 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L21/8238 , H01L23/532 , H01L23/58
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02131 , H01L21/02274 , H01L21/02362 , H01L21/31612 , H01L21/76801 , H01L21/76832 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

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