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1. 发明授权

US06261897B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06261897B1
公开(公告)日：2001-07-17
申请号：US09311530
申请日：1999-05-13
申请人： Tadashi Fukase , Masahiro Komuro
发明人： Tadashi Fukase , Masahiro Komuro
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10888
摘要： In a method of manufacturing a semiconductor device, MOS transistors are formed on a semiconductor substrate. Each of the MOS transistors includes impurity diffusion regions and a gate electrode. A first interlayer insulating film is deposited over the MOS transistors. Contact holes are opened in the first interlayer insulating film so as to reach the impurity diffusion regions. A conductor is deposited on an entire surface of the semiconductor substrate. The deposited conductor is etched back in order to form contact plugs only in the contact holes. Pad portions are formed only on the contact plugs by the use of a selective growth method. A capacitor is formed over the semiconductor substrate so as to be connected to the pad potions via capacitor contacts.
摘要翻译：在制造半导体器件的方法中，在半导体衬底上形成MOS晶体管。每个MOS晶体管包括杂质扩散区和栅电极。在MOS晶体管上沉积第一层间绝缘膜。接触孔在第一层间绝缘膜中打开以到达杂质扩散区。导体沉积在半导体衬底的整个表面上。将沉积的导体回蚀刻以仅在接触孔中形成接触塞。通过使用选择性生长方法仅在接触塞上形成垫部分。在半导体衬底上形成电容器，以通过电容器触点与焊盘部分连接。

2. 发明授权

US06876064B2 Semiconductor device having superior resistance to moisture 失效
标题翻译：具有优异的抗潮湿性的半导体装置
公开(公告)号：US06876064B2
公开(公告)日：2005-04-05
申请号：US10753326
申请日：2004-01-09
申请人： Akira Matumoto , Tadashi Fukase , Manabu Iguchi , Masahiro Komuro
发明人： Akira Matumoto , Tadashi Fukase , Manabu Iguchi , Masahiro Komuro
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/00 , H01L23/28 , H01L27/04 , H01L23/58
CPC分类号： H01L23/564 , H01L23/28 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.
摘要翻译：在半导体器件中，电路单元形成在内部，并且围绕周边形成围绕由金属层的壁构成的内部的密封环。在拐角处，密封圈除了沿着周边延伸的直线部分之外还包括向内延伸的直线部分，由此密封环形成为在每个拐角处具有小矩形平面图案的平面图案。

3. 发明授权

US08217516B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08217516B2
公开(公告)日：2012-07-10
申请号：US12477178
申请日：2009-06-03
申请人： Nobuaki Takahashi , Masahiro Komuro , Satoshi Matsui
发明人： Nobuaki Takahashi , Masahiro Komuro , Satoshi Matsui
IPC分类号： H01L23/24
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05684 , H01L2224/13009 , H01L2224/131 , H01L2224/13562 , H01L2224/1357 , H01L2224/13644 , H01L2224/13664 , H01L2224/17181 , H01L2924/00014
摘要： In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.
摘要翻译：在该半导体装置中，通孔形成在基板上，位于导电图案的下方。绝缘层位于通孔的底面。导电图案位于基板的一个表面侧。开口图案形成在位于通孔和导电图案之间的绝缘层中，其中从开口图案的周边到通孔的中心轴线的距离r3小于通孔中的距离r1 通孔。通过设置开口图案，导电图案在通孔的底面露出。凸块位于基板的背面侧，与贯通电极一体形成。

4. 发明授权

US07914300B2 Terminal mounting structure in electrical junction box 失效
标题翻译：电接线盒中的端子安装结构
公开(公告)号：US07914300B2
公开(公告)日：2011-03-29
申请号：US12866816
申请日：2009-06-01
申请人： Masahiro Akahori , Masatoshi Egawa , Hiroyuki Wakamatsu , Yousuke Okamoto , Makoto Sunohara , Masahiro Komuro
发明人： Masahiro Akahori , Masatoshi Egawa , Hiroyuki Wakamatsu , Yousuke Okamoto , Makoto Sunohara , Masahiro Komuro
IPC分类号： H01R12/00
CPC分类号： B60R16/04 , B60R16/0238 , H01R4/305 , H01R4/34 , H01R11/12
摘要： A structure for screw-tightening and connecting a terminal to an electrical junction box is provided. The terminal mounting structure in the electrical junction box ensures mounting operation with an insertion direction of the terminal obliquely oriented, and prevents heating of the terminal due to power supply. The terminal is secured and connected to a busbar of the junction box by a bolt, with a head and a shaft of the bolt inserted into a vertical opening and a horizontal notched hole of the terminal, respectively. A pair of opposed guiding walls are provided on a junction box body at both sides of the bolt. The guiding wall includes an entrance's side sloping surface obliquely extending from top to bottom, and a straight horizontal surface continuing to the sloping surface. The terminal includes a pair of outward projecting pieces at an upper portion to be slid on the sloping surface and the horizontal surface. A heat release portion extends integrally at an upper portion of a vertical plate portion of the terminal having the vertical opening. Linear indentations are provided on front and back surfaces of the heat release portion to be exposed outside.
摘要翻译：提供了一种用于螺丝紧固和将端子连接到电接线盒的结构。电接线盒中的端子安装结构确保了端子的插入方向倾斜定向的安装操作，并且防止由于供电引起的端子加热。端子通过螺栓固定并连接到接线盒的汇流条，螺栓的头部和轴分别插入端子的垂直开口和水平凹口孔中。一对相对的引导壁设置在螺栓两侧的接线盒主体上。引导壁包括从上到下倾斜延伸的入口侧倾斜表面和连续到倾斜表面的直的水平表面。该端子包括一对向上突出的突出片，该突出片在上部被滑动并在倾斜表面和水平表面上。散热部分在具有垂直开口的端子的垂直板部分的上部处一体地延伸。在放热部分的前表面和后表面上提供线性凹痕以暴露在外面。

5. 发明申请

US20070126085A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070126085A1
公开(公告)日：2007-06-07
申请号：US11602346
申请日：2006-11-21
申请人： Masaya Kawano , Koji Soejima , Nobuaki Takahashi , Yoichiro Kurita , Masahiro Komuro , Satoshi Matsui
发明人： Masaya Kawano , Koji Soejima , Nobuaki Takahashi , Yoichiro Kurita , Masahiro Komuro , Satoshi Matsui
IPC分类号： H01L23/48 , H01L21/58
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L23/562 , H01L23/642 , H01L25/50 , H01L2221/68345 , H01L2223/6622 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06572 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/10155 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes an interconnect member, a first semiconductor chip, a second semiconductor chip, a resin layer, an inorganic insulating layer, and a through electrode. The first semiconductor chip is mounted in a face-down manner on the interconnect member. The resin layer covers the side surface of the first semiconductor chip. This inorganic insulating layer is in contact with the back surface of the first semiconductor chip, and directly covers the back surface. Also, the inorganic insulating layer extends over the resin layer. The through electrode penetrates the inorganic insulating layer and the semiconductor substrate of the first semiconductor chip. The second semiconductor chip is mounted in a face-down manner on the inorganic insulating layer that covers the back surface of the first semiconductor chip in the uppermost layer.
摘要翻译：半导体器件包括互连部件，第一半导体芯片，第二半导体芯片，树脂层，无机绝缘层和贯通电极。第一半导体芯片以面朝下的方式安装在互连构件上。树脂层覆盖第一半导体芯片的侧表面。该无机绝缘层与第一半导体芯片的背面接触，直接覆盖背面。此外，无机绝缘层在树脂层上延伸。贯通电极穿透第一半导体芯片的无机绝缘层和半导体衬底。第二半导体芯片以面朝下的方式安装在覆盖最上层的第一半导体芯片的背面的无机绝缘层上。

6. 发明授权

US07833909B2 Method of manufacturing semiconductor device, and etching apparatus 有权
标题翻译：制造半导体器件的方法和蚀刻装置
公开(公告)号：US07833909B2
公开(公告)日：2010-11-16
申请号：US12385845
申请日：2009-04-21
申请人： Masahiro Komuro
发明人： Masahiro Komuro
IPC分类号： H01L21/311
CPC分类号： H01L21/308 , H01L21/67069 , Y10S438/944
摘要： Aimed at suppressing roughening in a circumferential portion of a layer to be etched in the process of removing a hard mask formed thereon, an etching apparatus of the present invention has a process chamber, an electrode, a stage, and a shadow ring, wherein the process chamber allows an etching gas to be introduced therein; the electrode is disposed in the process chamber, and is used for generating plasma by ionizing the etching gas; the stage is disposed in the process chamber, onto which a substrate is disposed; the shadow ring has an irregular pattern on the inner circumferential edge thereof, and is disposed in the process chamber and placed above the stage 30, so as to cover a circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner.
摘要翻译：为了在去除形成在其上的硬掩模的过程中抑制待蚀刻层的圆周部分的粗糙化，本发明的蚀刻装置具有处理室，电极，载物台和阴影环，其中，处理室允许在其中引入蚀刻气体; 电极设置在处理室中，用于通过电离蚀刻气体来产生等离子体; 该台设置在处理室中，其上设置有基板; 阴影环在其内周边缘上具有不规则图案，并且设置在处理室中并且放置在平台30上方，以便以非接触方式覆盖基板的周边部分和与其相邻的内部区域。

7. 发明授权

US06316328B1 Fabrication method for semiconductor device utilizing parallel alignment slits 失效
标题翻译：利用平行对准狭缝的半导体器件的制造方法
公开(公告)号：US06316328B1
公开(公告)日：2001-11-13
申请号：US09265467
申请日：1999-03-10
申请人： Masahiro Komuro
发明人： Masahiro Komuro
IPC分类号： H01L2176
CPC分类号： G03F7/70633 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A fabrication method for a semiconductor device is provided, which is able to increase pattern-to pattern lithography overlay accuracy. After a first layer made of a first material is formed, first and second slits serving as a first alignment mark are formed in the first layer. The first and second slits are spaced with a specific distance and are approximately parallel to each other. Each of the first and second slits is filled with a second material. Then, a second layer made of a third material is formed on the first layer. Subsequently, a mask is formed on the second layer. The mask has a first pattern serving as a second alignment mark. The second alignment mark is overlapped with the first and second slits serving as the first alignment mark. Preferably, the first alignment mark provides the main scale of a caliper, and the second alignment mark provides the vernier scale of the caliper.
摘要翻译：提供了一种用于半导体器件的制造方法，其能够增加图案到图案光刻覆盖精度。在形成由第一材料制成的第一层之后，在第一层中形成用作第一对准标记的第一和第二狭缝。第一和第二狭缝间隔一定距离并且彼此大致平行。第一和第二狭缝中的每一个都填充有第二材料。然后，在第一层上形成由第三材料制成的第二层。随后，在第二层上形成掩模。掩模具有用作第二对准标记的第一图案。第二对准标记与用作第一对准标记的第一和第二狭缝重叠。优选地，第一对准标记提供卡尺的主刻度，并且第二对准标记提供卡尺的游标刻度。

8. 发明授权

US08791567B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08791567B2
公开(公告)日：2014-07-29
申请号：US13494537
申请日：2012-06-12
申请人： Nobuaki Takahashi , Masahiro Komuro , Satoshi Matsui
发明人： Nobuaki Takahashi , Masahiro Komuro , Satoshi Matsui
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05684 , H01L2224/13009 , H01L2224/131 , H01L2224/13562 , H01L2224/1357 , H01L2224/13644 , H01L2224/13664 , H01L2224/17181 , H01L2924/00014
摘要： In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.
摘要翻译：在该半导体装置中，通孔形成在基板上，位于导电图案的下方。绝缘层位于通孔的底面。导电图案位于基板的一个表面侧。开口图案形成在位于通孔和导电图案之间的绝缘层中，其中从开口图案的周边到通孔的中心轴线的距离r3小于通孔中的距离r1 通孔。通过设置开口图案，导电图案在通孔的底面露出。凸块位于基板的背面侧，与贯通电极一体形成。

9. 发明授权

US07994048B2 Method of manufacturing a through electrode 有权
标题翻译：制造贯通电极的方法
公开(公告)号：US07994048B2
公开(公告)日：2011-08-09
申请号：US11765696
申请日：2007-06-20
申请人： Masahiro Komuro
发明人： Masahiro Komuro
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/147 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2221/68372 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/0554 , H01L2224/05555 , H01L2224/1147 , H01L2224/13009 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13144 , H01L2224/16 , H01L2224/32225 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06572 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04953 , H01L2924/1433 , H01L2924/15311 , H01L2924/30105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a silicon substrate, an insulative thick film is provided so as to be in contact with a surface of the silicon substrate and a side wall of a through hole penetrating the silicon substrate. An upper surface of a through plug is retreated to a lower level than an interface between the silicon substrate and the insulative thick film, thus to define a height gap. A first bump is then formed, which is connected to the retreated surface of the through plug and has a larger diameter than that of the through plug at the upper surface of the insulative thick film.
摘要翻译：提供了能够提供优异性能并且可以通过简单工艺制造的通孔。在包括硅衬底的硅衬垫中，提供绝缘厚膜以与硅衬底的表面和穿透硅衬底的通孔的侧壁接触。通孔的上表面被退回到比硅衬底和绝缘厚膜之间的界面更低的水平面，从而限定高度间隙。然后形成第一凸起，其连接到贯穿塞的后退表面，并且在绝缘厚膜的上表面处具有比通孔的直径更大的直径。

10. 发明申请

US20110003517A1 TERMINAL MOUNTING STRUCTURE IN ELECTRICAL JUNCTION BOX 失效
标题翻译：电气接线盒中的端子安装结构
公开(公告)号：US20110003517A1
公开(公告)日：2011-01-06
申请号：US12866816
申请日：2009-06-01
申请人： Masahiro Akahori , Masatoshi Egawa , Hiroyuki Wakamatsu , Yousuke Okamoto , Makoto Sunohara , Masahiro Komuro
发明人： Masahiro Akahori , Masatoshi Egawa , Hiroyuki Wakamatsu , Yousuke Okamoto , Makoto Sunohara , Masahiro Komuro
IPC分类号： H01R4/38
CPC分类号： B60R16/04 , B60R16/0238 , H01R4/305 , H01R4/34 , H01R11/12
摘要： A structure for screw-tightening and connecting a terminal to an electrical junction box is provided. The terminal mounting structure in the electrical junction box ensures mounting operation with an insertion direction of the terminal obliquely oriented, and prevents heating of the terminal due to power supply. The terminal is secured and connected to a busbar of the junction box by a bolt, with a head and a shaft of the bolt inserted into a vertical opening and a horizontal notched hole of the terminal, respectively. A pair of opposed guiding walls are provided on a junction box body at both sides of the bolt. The guiding wall includes an entrance's side sloping surface obliquely extending from top to bottom, and a straight horizontal surface continuing to the sloping surface. The terminal includes a pair of outward projecting pieces at an upper portion to be slid on the sloping surface and the horizontal surface. A heat release portion extends integrally at an upper portion of a vertical plate portion of the terminal having the vertical opening. Linear indentations are provided on front and back surfaces of the heat release portion to be exposed outside.
摘要翻译：提供了一种用于螺丝紧固和将端子连接到电接线盒的结构。电接线盒中的端子安装结构确保了端子的插入方向倾斜定向的安装操作，并且防止由于供电引起的端子加热。端子通过螺栓固定并连接到接线盒的汇流条，螺栓的头部和轴分别插入端子的垂直开口和水平凹口孔中。一对相对的引导壁设置在螺栓两侧的接线盒主体上。引导壁包括从上到下倾斜延伸的入口侧倾斜表面和连续到倾斜表面的直的水平表面。该端子包括一对向上突出的突出片，该突出片在上部被滑动并在倾斜表面和水平表面上。散热部分在具有垂直开口的端子的垂直板部分的上部处一体地延伸。在放热部分的前表面和后表面上提供线性凹痕以暴露在外面。

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