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    • 2. 发明授权
    • Method for forming a storage node in a semiconductor memory using ion
implantation to form a smooth amorphous polycrystalline film
    • 在半导体存储器中使用离子注入形成存储节点以形成平滑非晶多晶膜的方法
    • US5773342A
    • 1998-06-30
    • US856801
    • 1997-05-15
    • Tadashi Fukase
    • Tadashi Fukase
    • H01L21/265H01L21/8242H01L27/108
    • H01L27/10852
    • In a semiconductor memory, for forming a storage node of an information storage capacitor formed above a semiconductor substrate, an interlayer insulator film is formed above the semiconductor substrate, and a contact hole is formed to penetrate through the interlayer insulator film and to reach the semiconductor substrate. A polysilicon film is deposited to fill the contact hole and to cover the interlayer insulator film, and ions are implanted into the polysilicon film to convert a surface layer of the polysilicon film into an amorphous state, so that the surface of polysilicon film is smoothened. On the polysilicon film, a resist mask for patterning of the storage node is formed by a photolithography, and, and the polysilicon film is etched using the resist mask to form the storage node.
    • 在半导体存储器中,为了形成在半导体衬底上形成的信息存储电容器的存储节点,在半导体衬底上方形成层间绝缘膜,并且形成接触孔以穿透层间绝缘膜并到达半导体 基质。 沉积多晶硅膜以填充接触孔并覆盖层间绝缘膜,并将离子注入到多晶硅膜中以将多晶硅膜的表面层转变为非晶态,使得多晶硅膜的表面平滑化。 在多晶硅膜上,通过光刻法形成用于图案化存储节点的抗蚀剂掩模,并且使用抗蚀剂掩模蚀刻多晶硅膜以形成存储节点。
    • 3. 发明授权
    • Method of manufacturing semiconductor integrated circuit device having a
capacitor electrode
    • 具有电容器电极的半导体集成电路器件的制造方法
    • US5691222A
    • 1997-11-25
    • US745849
    • 1996-11-12
    • Tadashi Fukase
    • Tadashi Fukase
    • H01L21/822H01L21/8239H01L21/8242H01L27/04H01L27/108
    • H01L27/10852H01L27/1052
    • A method of manufacturing a semiconductor integrated circuit device which stores information by storing charges in a capacitor portion formed on a semiconductor substrate is provided. This method includes the steps of depositing a conductive film for forming a lower electrode of storage node capacitor portion on an insulating interlayer film formed with a contact hole for forming a contact that connects the capacitor portion with the substrate, depositing a cap oxide film on the conductive film and planarizing the cap oxide film, applying a resist on the planarized cap oxide film to a uniform thickness and forming a pattern mask of the storage node capacitor portion from the resist, etching the cap oxide film and the conductive film by using the pattern mask as a mask, and forming a lower electrode of the storage node capacitor portion by removing the cap oxide film.
    • 提供一种制造半导体集成电路器件的方法,该半导体集成电路器件通过将电荷存储在形成在半导体衬底上的电容器部分中来存储信息。 该方法包括以下步骤:将形成存储节点电容器部分的下电极的导电膜沉积在形成有用于形成连接电容器部分与基板的接触的接触孔的绝缘层间膜上,在其上沉积氧化膜 将平坦化的氧化膜上的抗蚀剂施加到均匀的厚度,并且从抗蚀剂形成存储节点电容器部分的图案掩模,通过使用图案蚀刻帽氧化物膜和导电膜, 掩模作为掩模,并且通过去除盖氧化膜形成存储节点电容器部分的下电极。
    • 5. 发明授权
    • Method of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US06261897B1
    • 2001-07-17
    • US09311530
    • 1999-05-13
    • Tadashi FukaseMasahiro Komuro
    • Tadashi FukaseMasahiro Komuro
    • H01L218242
    • H01L27/10855H01L27/10814H01L27/10888
    • In a method of manufacturing a semiconductor device, MOS transistors are formed on a semiconductor substrate. Each of the MOS transistors includes impurity diffusion regions and a gate electrode. A first interlayer insulating film is deposited over the MOS transistors. Contact holes are opened in the first interlayer insulating film so as to reach the impurity diffusion regions. A conductor is deposited on an entire surface of the semiconductor substrate. The deposited conductor is etched back in order to form contact plugs only in the contact holes. Pad portions are formed only on the contact plugs by the use of a selective growth method. A capacitor is formed over the semiconductor substrate so as to be connected to the pad potions via capacitor contacts.
    • 在制造半导体器件的方法中,在半导体衬底上形成MOS晶体管。 每个MOS晶体管包括杂质扩散区和栅电极。 在MOS晶体管上沉积第一层间绝缘膜。 接触孔在第一层间绝缘膜中打开以到达杂质扩散区。 导体沉积在半导体衬底的整个表面上。 将沉积的导体回蚀刻以仅在接触孔中形成接触塞。 通过使用选择性生长方法仅在接触塞上形成垫部分。 在半导体衬底上形成电容器,以通过电容器触点与焊盘部分连接。
    • 10. 发明授权
    • Fabrication process of a semiconductor device with a wiring structure
    • 具有布线结构的半导体器件的制造工艺
    • US5578524A
    • 1996-11-26
    • US413868
    • 1995-03-29
    • Tadashi FukaseTakehiko Hamada
    • Tadashi FukaseTakehiko Hamada
    • H01L21/28H01L21/768H01L23/522H01L21/283H01L21/31
    • H01L21/76897H01L21/76832H01L21/76834
    • An intermediate insulation layer provided between a wiring of gate electrodes on a semiconductor substrate and a wiring formed in an upper layer includes a first interlayer insulation layer, a silicon rich oxide layer stacked on the first interlayer insulation layer and containing excessive silicon atom, and a second interlayer insulation layer stacked over the silicon rich oxide layer. Processes are provided for selectively performing dry etching for the insulation layers in order to simultaneously and easily form a self-aligned type contact hole on the diffusion layer position at the gap between oppositely arranged gate electrodes and a contact hole on the wiring of the predetermined gate electrode. In this manner, on the diffusion layer and the wiring of the gate electrode, the self-align contact hole and the contact hole are formed in the same process. This permits elimination of the need for margins in formation of the contact hole in the semiconductor device adapted for ultra-high packing density.
    • 设置在半导体基板上的栅电极的布线和形成在上层中的布线之间的中间绝缘层包括层叠在第一层间绝缘层上并含有过量硅原子的第一层间绝缘层,富硅氧化物层,以及 层叠在富硅氧化物层上的第二层间绝缘层。 提供了用于选择性地对绝缘层进行干蚀刻的工艺,以便在相对布置的栅电极之间的间隙处的扩散层位置和预定栅极的布线上的接触孔中同时且容易地形成自对准型接触孔 电极。 以这种方式,在扩散层和栅电极的布线上,以相同的工艺形成自对准接触孔和接触孔。 这允许消除在适合于超高封装密度的半导体器件中形成接触孔的边缘的需要。