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1. 发明授权

US08551830B2 Semiconductor integrated circuit switch matrix 有权
标题翻译：半导体集成电路开关矩阵
公开(公告)号：US08551830B2
公开(公告)日：2013-10-08
申请号：US12110800
申请日：2008-04-28
申请人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L27/12 , H01L21/8221 , H01L27/0688 , Y10S257/903
摘要： There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.
摘要翻译：提供电路面积小，布线长度短的小型半导体集成电路。半导体集成电路构造为多层结构，并且设置有第一半导体层，形成在第一半导体层中的第一半导体层晶体管，布置在第一半导体层上并且其中金属线为形成，沉积在布线层上的第二半导体层和形成在第二半导体层中的第二半导体层晶体管。注意，第一半导体层晶体管的栅极绝缘膜的绝缘几乎等于第二半导体层晶体管的栅极绝缘膜的绝缘，并且通过自由基氧化形成第二半导体层晶体管的栅极绝缘膜或自由基氮化。

2. 发明申请

US20060017101A1 Semiconductor integrated circuit and manufacturing method of the same 有权
标题翻译：半导体集成电路及其制造方法相同
公开(公告)号：US20060017101A1
公开(公告)日：2006-01-26
申请号：US11182026
申请日：2005-07-15
申请人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L27/12 , H01L21/8221 , H01L27/0688 , Y10S257/903
摘要： There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.
摘要翻译：提供电路面积小，布线长度短的小型半导体集成电路。半导体集成电路构造为多层结构，并且设置有第一半导体层，形成在第一半导体层中的第一半导体层晶体管，布置在第一半导体层上并且其中金属线为形成，沉积在布线层上的第二半导体层和形成在第二半导体层中的第二半导体层晶体管。注意，第一半导体层晶体管的栅极绝缘膜的绝缘几乎等于第二半导体层晶体管的栅极绝缘膜的绝缘，并且通过自由基氧化形成第二半导体层晶体管的栅极绝缘膜或自由基氮化。

3. 发明申请

US20060017071A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060017071A1
公开(公告)日：2006-01-26
申请号：US11182018
申请日：2005-07-15
申请人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/11807
摘要： There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality of transistors formed respectively in a plurality of semiconductor layers and a plurality of logic blocks formed in each of the plurality of semiconductor layers and connected to each of the plurality of signal lines. The first switch block is a programmable switch block capable of changing the connection topology among the plurality of signal lines.
摘要翻译：提供了电路面积小，布线长度短的高性能半导体集成电路。半导体集成电路构造成多层结构，并且设置有用于通过分别形成在多个半导体层中的多个晶体管和多个形成的多个逻辑块来在多个信号线之间切换连接的开关块在多个半导体层的每一个中并连接到多个信号线中的每一个。第一开关块是能够改变多个信号线之间的连接拓扑的可编程开关块。

4. 发明申请

US20080318370A1 Semiconductor Integrated Circuit Switch Matrix 有权
标题翻译：半导体集成电路开关矩阵
公开(公告)号：US20080318370A1
公开(公告)日：2008-12-25
申请号：US12110800
申请日：2008-04-28
申请人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： H01L21/336
CPC分类号： H01L27/12 , H01L21/8221 , H01L27/0688 , Y10S257/903
摘要： There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.
摘要翻译：提供电路面积小，布线长度短的小型半导体集成电路。半导体集成电路构造为多层结构，并且设置有第一半导体层，形成在第一半导体层中的第一半导体层晶体管，布置在第一半导体层上并且其中金属线为形成，沉积在布线层上的第二半导体层和形成在第二半导体层中的第二半导体层晶体管。注意，第一半导体层晶体管的栅极绝缘膜的绝缘几乎等于第二半导体层晶体管的栅极绝缘膜的绝缘，并且通过自由基氧化形成第二半导体层晶体管的栅极绝缘膜或自由基氮化。

5. 发明授权

US07193434B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07193434B2
公开(公告)日：2007-03-20
申请号：US11182018
申请日：2005-07-15
申请人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： H03K19/173
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/11807
摘要： There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality of transistors formed respectively in a plurality of semiconductor layers and a plurality of logic blocks formed in each of the plurality of semiconductor layers and connected to each of the plurality of signal lines. The first switch block is a programmable switch block capable of changing the connection topology among the plurality of signal lines.
摘要翻译：提供了电路面积小，布线长度短的高性能半导体集成电路。半导体集成电路构造成多层结构，并且设置有用于通过分别形成在多个半导体层中的多个晶体管和多个形成的多个逻辑块来在多个信号线之间切换连接的开关块在多个半导体层的每一个中并连接到多个信号线中的每一个。第一开关块是能够改变多个信号线之间的连接拓扑的可编程开关块。

6. 发明授权

US07667276B2 Semiconductor integrated circuit switch matrix 有权
标题翻译：半导体集成电路开关矩阵
公开(公告)号：US07667276B2
公开(公告)日：2010-02-23
申请号：US11182026
申请日：2005-07-15
申请人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Tadahiro Ohmi , Koji Kotani , Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/12 , H01L21/8221 , H01L27/0688 , Y10S257/903
摘要： There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.
摘要翻译：提供电路面积小，布线长度短的小型半导体集成电路。半导体集成电路构造为多层结构，并且设置有第一半导体层，形成在第一半导体层中的第一半导体层晶体管，布置在第一半导体层上并且其中金属线为形成，沉积在布线层上的第二半导体层和形成在第二半导体层中的第二半导体层晶体管。注意，第一半导体层晶体管的栅极绝缘膜的绝缘几乎等于第二半导体层晶体管的栅极绝缘膜的绝缘，并且通过自由基氧化形成第二半导体层晶体管的栅极绝缘膜或自由基氮化。

7. 发明授权

US07566936B2 Complementary MIS device 失效
标题翻译：互补MIS设备
公开(公告)号：US07566936B2
公开(公告)日：2009-07-28
申请号：US11606181
申请日：2006-11-30
申请人： Tadahiro Ohmi , Koji Kotani , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Koji Kotani , Shigetoshi Sugawa
IPC分类号： H01L29/76
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L27/092 , H01L27/0922 , H01L29/66795 , H01L29/7851
摘要： A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode formed thereon, wherein the size and the shape of the foregoing structure is set such that the carrier mobility is balanced between the p-channel MOS transistor and the n-channel MOS transistor.
摘要翻译： CMOS器件包括具有形成在硅衬底（100）表面上并具有不同晶体表面的结构的p沟道MOS晶体管和n沟道MOS晶体管，形成在这种结构上的高质量栅极绝缘膜通过微波等离子体处理和形成在其上的栅电极，其中上述结构的尺寸和形状被设置为使得载流子迁移率在p沟道MOS晶体管和n沟道MOS晶体管之间平衡。

8. 发明授权

US5959484A Feed back circuit 失效
标题翻译：回馈电路
公开(公告)号：US5959484A
公开(公告)日：1999-09-28
申请号：US807374
申请日：1997-02-27
申请人： Tadahiro Ohmi , Tadashi Shibata , Hiroaki Terada , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Hiroaki Terada , Koji Kotani
IPC分类号： G06G7/60 , H01L21/8234 , H01L27/088 , H03K3/356 , H03K19/08 , H03K19/20
CPC分类号： H03K19/0813
摘要： A feedback circuit is provided which is capable of realizing handshake functions, flip flop functions, and other functions using a smaller number of elements and chip surface. The threshold circuit is provided with an electrode which is electrically floating and a plurality of input electrodes which are connected with the floating electrode via capacity elements, and the circuit has a mechanism for essentially determining the potential of the floating electrode by means of the potentials applied to the input electrodes, and the output of the circuit is determined by the potential of the floating gate; the output of the threshold circuit is connected to at least one of the plurality of input electrodes, either directly, or via at least one circuit of some type.
摘要翻译：提供了一种反馈电路，其能够使用较少数量的元件和芯片表面来实现握手功能，触发器功能和其他功能。阈值电路设置有电浮动的电极和通过电容元件与浮动电极连接的多个输入电极，并且电路具有用于通过施加的电位基本上确定浮置电极的电位的机构到输入电极，并且电路的输出由浮栅的电位确定; 阈值电路的输出直接或经由某种类型的至少一个电路连接到多个输入电极中的至少一个。

9. 发明授权

US5661421A Semiconductor integrated data matching circuit 失效
标题翻译：半导体集成数据匹配电路
公开(公告)号：US5661421A
公开(公告)日：1997-08-26
申请号：US507473
申请日：1995-09-29
申请人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
发明人： Tadahiro Ohmi , Tadashi Shibata , Koji Kotani
IPC分类号： G06F7/04 , G06G7/60 , G06N3/063 , H03K19/21 , A03K5/22
CPC分类号： G06N3/0635
摘要： A semiconductor integrated circuit for effecting data matching at high speed is provided in a simple circuit. The semiconductor integrated circuit includes a first input terminal and a second input terminal to which first and second voltage signals representing first and second values are inputted, respectively, and an output terminal. A predetermined output signal is produced at the output terminal when the difference between the first and second values is smaller than a predetermined difference value. The semiconductor integrated circuit of this invention comprises first and second inverters, each inverter comprising neuron MOS transistors having a plurality of input gates. The first and second signals or, first and second processed signals obtained by applying predetermined processing to the first and second signals, are inputted to at least one of the input gates of the inverters.
摘要翻译： PCT No.PCT / JP94 / 00263 Sec。 371 1995年9月29日第 102（e）1995年9月29日PCT PCT 1994年2月22日PCT公布。 WO94 / 19761 PCT出版物日期1994年9月1日在简单的电路中提供用于高速实现数据匹配的半导体集成电路。半导体集成电路包括分别输入表示第一和第二值的第一和第二电压信号的第一输入端和第二输入端和输出端。当第一和第二值之间的差小于预定的差值时，在输出端产生预定的输出信号。本发明的半导体集成电路包括第一和第二反相器，每个反相器包括具有多个输入门的神经元MOS晶体管。通过对第一和第二信号应用预定处理而获得的第一和第二信号或第一和第二处理信号被输入至反相器的至少一个输入门。

10. 发明授权

US07296048B2 Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
标题翻译：用于算术处理和算术处理方法的半导体电路
公开(公告)号：US07296048B2
公开(公告)日：2007-11-13
申请号：US10641788
申请日：2003-08-15
申请人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
发明人： Tadahiro Ohmi , Makoto Imai , Toshiyuki Nozawa , Masanori Fujibayashi , Koji Kotani , Tadashi Shibata , Takahisa Nitta
IPC分类号： G06F7/52
CPC分类号： G06F7/4824 , G06F7/506
摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing.There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1–3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
摘要翻译：提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

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