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1. 发明专利

JPH04249983A DIGITAL PROCESSING GHOST ELIMINATION DEVICE 失效
公开(公告)号：JPH04249983A
公开(公告)日：1992-09-04
申请号：JP3440191
申请日：1991-02-28
申请人： TOSHIBA CORP
发明人： MATSUE HIROSHI , IGA HIROYUKI , MURAKAMI JUNZO
IPC分类号： H04N5/21 , H03H15/00 , H03H17/00 , H03H21/00 , H04B3/04
摘要： PURPOSE:To obtain the digital processing ghost elimination device brought into practical use through the reduction of a circuit scale. CONSTITUTION:An output of a subtractor 29 is given to equalization units connected in cascade. Each equalization unit delays an inputted signal by a variable delay circuit in a delay quantity in response to the ghost delay time and gives the result to a next stage equalization unit. The output of a transversal filter of each equalization unit is added to an output from other equalization unit and the output of an adder of a first stage is given to the subtractor 29 as a ghost cancel signal. The subtractor 29 subtracts the ghost cancel signal from a television signal to output an output from which ghost is eliminated. Thus, the ghost in the delay time of a wide range is eliminated with less number of taps.

2. 发明专利

JPS61234139A PHASE LOCKED LOOP 失效
公开(公告)号：JPS61234139A
公开(公告)日：1986-10-18
申请号：JP7475085
申请日：1985-04-09
申请人： TOSHIBA CORP , JAPAN BROADCASTING CORP
发明人： MURAKAMI JUNZO , YAMAZAKI NOBORU , YOROZU MASATOSHI
IPC分类号： H04L7/033 , H04N5/12
摘要： PURPOSE:To obtain a reproducing clock which is less in phase jitters caused by noises by inserting an amplitude limiter between a phase comparator and loop filter. CONSTITUTION:When a noise component is contained in the input signal of a phase comparator 16, the output of the comparator 16 is changeable over the full range of -256/256-256/256 depending upon the scale of the noise. An amplitude limiter 6 is provided to suppress such an output which depends upon noise components and its amplitude limiting range is set to an extent which is almost equal to the amplitude changing range, -64/256-64/256, of phase error signals produceable in the output of the phase comparator 16 when no noise component exists in the input signal. Therefore, the amplitude changing range of a signal supplied to a loop filter 7 never exceeds the amplitude changing range of the original phase error signal caused by the phase error of a sampling clock, even if the noise of any instantaneous amplitude is mixed in the input signal.

3. 发明专利

JPS61234138A PHASE LOCKED LOOP 失效
公开(公告)号：JPS61234138A
公开(公告)日：1986-10-18
申请号：JP7474985
申请日：1985-04-09
申请人： TOSHIBA CORP , JAPAN BROADCASTING CORP
发明人： MURAKAMI JUNZO , YAMAZAKI NOBORU , YOROZU MASATOSHI
IPC分类号： H04L7/033 , H04L7/08 , H04N5/10 , H04N5/12
摘要： PURPOSE:To remarkably shorten the time required until phase lock is established by forcedly performing initial leading-in operations by resetting a frequency dividing circuit when an asynchronous state continuously occurs over a time period longer than a certain degree of period. CONSTITUTION:A frame pulse (FP) phase comparator circuit 4 performs phase comparison between a detected FP point and the specific point of an internal FP signal which is the output of a frequency dividing circuit 12 and outputs '0', when the difference between both points is within the range of + or -1 clock. The circuit 4 outputs '1' if the difference between both points is out of the range of + or -1 clock. A discriminating circuit 13 observes the output of the FP phase comparator circuit 4 and, when '1' is continuously observed by a previously fixed number of times (for example: 8 times), outputs '1'. A reset pulse generating circuit 14 is set to a waiting state when the output of the discriminating circuit 13 changes from '0' to '1' and generates a reset pulse 15 at the timing of first arriving detected FP point. Then a loop filter 6 and frequency dividing circuits 11 and 12 are reset to prescribed initial states.

4. 发明专利

JPH07226783A SAMPLING PHASE SYNCHRONIZATION DEVICE 失效
公开(公告)号：JPH07226783A
公开(公告)日：1995-08-22
申请号：JP1877894
申请日：1994-02-16
申请人： TOSHIBA CORP
发明人： NAMEKATA MINORU , MURAKAMI JUNZO
IPC分类号： H04L27/38 , H04B3/06 , H04J3/06 , H04L7/00 , H04L25/08
摘要： PURPOSE:To allow the sampling phase synchronization device for Viterbi equalizer to provide a sampling timing at which the reliability of a demodulation code demodulated by a Viterbi equalizer is best under a multi-path fading transmission line environment specific to mobile communication. CONSTITUTION:A reception signal 13 is orthogonally transformed by an orthogonal transform section 15 in a receiver 14 and becomes a complex base band signal 16. The complex base band signal is given to an oversampling section 17, in which the signal becomes a discrete signal series 18. The discrete signal series 18 is inputted to a transmission line impulse response estimate section 114, in which a transmission line impulse response 115 is estimated. A normalized undesired signal power 117 is calculated by the transmission line impulse response 115 and an average normalized undesired signal power 121 is calculated in addition to the normalized undesired signal power 117. Thus, the average normalized undesired signal power is calculated, an optimum sampling reference signal 123 is decided, the complex base band discrete reception signal series 110 subjected to oversampling is thinned and the result is inputted to the Viterbi equalizer.

5. 发明专利

JPH04249982A DIGITAL PROCESSING GHOST ELIMINATION DEVICE 失效
公开(公告)号：JPH04249982A
公开(公告)日：1992-09-04
申请号：JP3434891
申请日：1991-02-28
申请人： TOSHIBA CORP
发明人： MATSUE HIROSHI , IGA HIROYUKI , MURAKAMI JUNZO
IPC分类号： H04N5/21
摘要： PURPOSE:To realize the digital processing ghost elimination device brought into practical use through the reduction of a circuit scale. CONSTITUTION:An output of a subtractor 29 is given to a 1st input terminal I1 of equalization units 21, 22, 23, 24 connected in parallel. A variable delay circuit of each equalization unit delays an inputted signal by an equalization quantity in response to a delay time of ghost and the result is given to a transversal filter. An output of the transversal filter is added to an output from other equalization unit and an output of an adder at a first stage is given to a subtractor 29 as a ghost cancellation signal. The subtractor 29 subtracts the ghost cancel signal from a television signal to output an output from which ghost is eliminated. Thus, the ghost in the delay time of a wide range is eliminated with less number of taps.

6. 发明专利

JPS61248674A DETECTION CIRCUIT FOR FRAME TIMING 失效
公开(公告)号：JPS61248674A
公开(公告)日：1986-11-05
申请号：JP8882285
申请日：1985-04-26
申请人： TOSHIBA CORP
发明人： IGA HIROYUKI , MURAKAMI JUNZO
IPC分类号： H04N5/10 , H04N5/08 , H04N7/00 , H04N7/015
摘要： PURPOSE:To make it possible to detect a high definition/high stable frame timing even in a low S/N time by integrating a binary signal which represents the state that a prescribed line is detected coarsely and the state that it is not detected, clearing an integrator when non-detecting states are continuously occurred by prescribed times and generating a pulse when the output of the integrator exceeds a prescribed value. CONSTITUTION:Using the binary signal which represents a detecting state that the prescribed line representing the frame timing is coarsely detected and the non-detecting state, the binary signal is integrated at an integrator 4a and when the non-detecting states are occurred by the prescribed times continuously, the integrator 4a is cleared and when the output of the integrator 4a is exceeded over the prescribed value, the pulse which represents the state is generated. For example, the output signal f of a 606 line coarsing detection circuit 1 is supplied to the OR gate 33 of a clear circuit 3a, a 1CK delay circuit 31 and an AND gate 2. The outputs Q1-Q10 of the counter 4a are supplied respectively to the A-inputs A1-A10 of a comparator 5 and the B-inputs (B1-B10) of the comparator 5 are connected with a slice level setting circuit 6. And the output signal of the 606 line coarsing detection circuit 1 is integrated at the counter 4a and the integrated result is compared with the prescribed value.

7. 发明专利

JPS61152173A GHOST ERASING DEVICE 失效
公开(公告)号：JPS61152173A
公开(公告)日：1986-07-10
申请号：JP27326684
申请日：1984-12-26
申请人： TOSHIBA CORP
发明人： IGA HIROYUKI , MURAKAMI JUNZO , MATSUE HIROSHI
IPC分类号： H04N5/21 , H04B3/06
摘要： PURPOSE:To use transversal filters with a small number of taps to improve the ghost erasing capacity by performing an operation while shifting a section by a minimum delay unit successively and detecting the section, where the operation result is maximum, to determine a delay quantity. CONSTITUTION:This device consists of equalizing circuit units 64 which consists of tap gain variable transversal filters 62 and variable delay circuits 61, a subtractor 63 which subtracts outputs of units 64 from the input signal of a terminal 11 and outputs the subtraction result to a terminal 15, a control part 13 which controls tap gains of filters 62 so that an error signal obtained from the output of the subtractpr 63 and a reference waveform is falt, and a delay quantity determining part 17 which controls the circuits 61 so that the delay quantity determined by the error waveform obtained in the control part 13 is obtained. In the determining part 17, the operation is performed by a means 72 with respect to the error waveform having an extent corresponding to the number of taps of filters 62 while shifting the section by a minimum delay time unit successively, and the section where the operation result is maximum is detected by a circuit 73, and circuits 61 are so controlled that the detected section enters into filters 62.

8. 发明专利

JPS61152172A GHOST ERASING DEVICE 失效
公开(公告)号：JPS61152172A
公开(公告)日：1986-07-10
申请号：JP27326584
申请日：1984-12-26
申请人： TOSHIBA CORP
发明人： MATSUE HIROSHI , IGA HIROYUKI , MURAKAMI JUNZO
IPC分类号： H04N5/21 , H04B3/06
摘要： PURPOSE:To determine a delay quantity quickly and accurately to improve the practicality by performing the operation, which determines an optimum delay quantity of a variable delay circuit, in every certain section corresponding to the equalization range of an equalizing circuit unit. CONSTITUTION:A subtractor 63 subtracts outputs of equalizing circuit units 64, which consist of variable delay circuits 61 and variable tap gain transversal filters 62, from the input signal of an input terminal 11 and outputs the subtraction result to an output terminal 15. A control part 13 controls tap gains of filters 62 so that an error waveform obtained from the output of the subtractor 63 and a reference waveform is flat, and a delay quantity determining part 17 controls circuits 61 so that the delay quantity of circuits 61 is equal to the delay quantity determined in accordance with the error waveform of the control part 13. In the determining part 17, a intra-section error operating means 72 performs a prescribed operation of the error waveform having an extent corresponding to the number taps of the filter 62 in each certain section corresponding to the equalization range of the unit 64, and the section where the operation result is maximum is detected by a detecting circuit 73, and the circuit 61 is so controlled that this detected section enters into the filter 62.

9. 发明专利

JPH0795163A DATA TRANSMITTER 失效
公开(公告)号：JPH0795163A
公开(公告)日：1995-04-07
申请号：JP23393193
申请日：1993-09-20
申请人： TOSHIBA CORP
发明人： MATSUSHIMA TOMOKO , NAKAJIMA NOBUYASU , MURAKAMI JUNZO
IPC分类号： H04L1/00 , H04B14/04
摘要： PURPOSE:To provide the data transmitter in which data are efficiently sent against a periodic error. CONSTITUTION:The transmitter is provided with a coding means 1 coding an information series to obtain a transmission data series, a transmission means 3 sending the transmission data series to a receiver side, a decoding means 5 receiving the signal sent by the transmission means 3 and decoding the received signal into a decoded data series, and error timing estimate means 6, 7 receiving at least one of the reception signal, the decoded data series, and output from the decoding means 5 other than the decoded data series to estimate a timing when an error takes place in the received signal, and at least one of the decoding and coding methods is corrected based on an error timing estimated by the error timing estimate means 6, 7.

10. 发明专利

JPH02256323A PHASE LOCKED TYPE MAXIMUM LIKELIHOOD DECODER 失效
公开(公告)号：JPH02256323A
公开(公告)日：1990-10-17
申请号：JP31211589
申请日：1989-11-29
申请人： TOSHIBA CORP
发明人： SERIZAWA MUTSUMI , MURAKAMI JUNZO
IPC分类号： H03M13/23
摘要： PURPOSE:To operate the decoder excellently even with low S/N by calculating a likelihood to a partial series sent from a sender side, and selecting the partial series having a maximum likelihood. CONSTITUTION:Suppose that all signal series stored in signal series storage sections 57A, 57B,... are sent respectively, then a series of a phase error is decided definitely by phase error detection sections 69A, 69B,.... When the shift quantity of a phase of a carrier is decided, a likelihood relating to the case that each of all the data series to be sent is sent is decided definitely with likelihood function calculation sections 59A, 59B,.... When the likelihood relating to all transmission data able to be sent is calculated, a maximum likelihood is selected by a comparison and selection section 61 to estimate the maximum possibility of which series is transmitted among signal series capable of being transmitted. Moreover, the shift of the phase of the carrier of a received signal is estimated definitely.

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