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1. 发明专利

JPH07193732A GHOST REMOVING DEVICE 失效
公开(公告)号：JPH07193732A
公开(公告)日：1995-07-28
申请号：JP33170393
申请日：1993-12-27
申请人： TOSHIBA CORP
发明人： ISHII AKIRA , IGA HIROYUKI
IPC分类号： H04N5/21
摘要： PURPOSE:To provide a ghost removing device which is inexpensive and having small circuit size and enabled to be mounted also on a compact television. CONSTITUTION:A composite video signal is supplied to an A/D conversion circuit 2 and a timing signal generating circuit 34. The circuit 34 prepares a write signal and a read signal for waveform memories A30, A31 and an addition/subtraction switching signal for an adding/subtracting circuit 33 by using a horizontal/vertical synchronizing signal. A control circuit 38 conducts the arithmetic processing of a waveform read out of the memory A30, prepares a ghost canceling signal and writes a ghost canceling signal for a horizontal synchronizing signal HSYNC in the memory A30 and a color burst canceling signal in the memory B31. The written signals are read out by a reading signal supplied from the circuit 34 and the video signal and the canceling signals are added/subtracted by a substructing circuit 32 and the adding/subtracting circuits 33 to remove a ghost.

2. 发明专利

JPH06178161A AUTOMATIC EQUALIZER 失效
公开(公告)号：JPH06178161A
公开(公告)日：1994-06-24
申请号：JP33194392
申请日：1992-12-11
申请人： TOSHIBA CORP
发明人： IGA HIROYUKI
IPC分类号： H04N5/21 , H03H15/00 , H03H17/00 , H03H21/00 , H04B3/04
摘要： PURPOSE:To compress the circuit scale of the whole device by compressing that of an equalization circuit and to reduce a cost. CONSTITUTION:This automatic equalizer is equipped with a TF 7c for I axis and a TF 11 for Q axis. The TF 7c consists of TFs of 128 taps in which a tap gap is set at T/2, and coefficients Ci,-6 to C1,121 are set as tap coefficients, respectively. On the other hand, the TF 11 consists of TFs of 16 taps provided with tap coefficients CQ,-6 to CQ,9. The output signal of the TF 11 is supplied to a variable delay element 12, and the variable delay element 12 delays an inputted signal by prescribed time. Linear distortion including a ghost can be eliminated from a digital multiplex signal by adding a main signal delayed by six taps by a delay element 7g on a compensation signal from the variable delay element 12 by an adder 7f.

3. 发明专利

JPH066719A PICTURE SIGNAL PROCESSOR 失效
公开(公告)号：JPH066719A
公开(公告)日：1994-01-14
申请号：JP15698892
申请日：1992-06-16
申请人： TOSHIBA CORP
发明人： YAMADA MASAHIRO , IGA HIROYUKI , HOSHINO KIYOSHI
IPC分类号： H04N5/46 , H04N7/00 , H04N7/015 , H04N9/00
摘要： PURPOSE:To obtain a picture signal processor capable of picture signal processing for various broadcasting media by a simple constitution and having economically profitable characteristics. CONSTITUTION:The picture signal processor is provided with an arithmetic means 53 for executing arithmetic processing for decoding inputted picture data based upon signal processing algorithm constituted of a combination of plural programs and a control means 35 for selecting the combination of plural programs to be applied to the means 53 so as not to exceed the maximum signal processing capacity of the means 53.

4. 发明专利

JPH05347738A 失效
公开(公告)号：JPH05347738A
公开(公告)日：1993-12-27
申请号：JP15459192
申请日：1992-06-15
申请人： TOSHIBA CORP
发明人： IGA HIROYUKI , YAMADA MASAHIRO
IPC分类号： H04N5/46 , H04N7/00 , H04N7/015 , H04N9/00
摘要： PURPOSE:To provide an image signal processor which can shorten the time required for the selection of channels through the end of the decoding processing by transferring a decoding program to a DSP decoder in parallel to another signal processing operation. CONSTITUTION:The deciding result of the system is read out of a system memory 55 for the image data selected by a 1st selector 51. Then a program is read out of a program ROM 60 based on the deciding result of the system and then transferred to a DSP decoder 59. The system of the optional image data selected by an input selector 50a is decided while the image data selected by the selector 51 are decoded. This deciding result is written into the memory 55.

5. 发明专利

JPH04249983A DIGITAL PROCESSING GHOST ELIMINATION DEVICE 失效
公开(公告)号：JPH04249983A
公开(公告)日：1992-09-04
申请号：JP3440191
申请日：1991-02-28
申请人： TOSHIBA CORP
发明人： MATSUE HIROSHI , IGA HIROYUKI , MURAKAMI JUNZO
IPC分类号： H04N5/21 , H03H15/00 , H03H17/00 , H03H21/00 , H04B3/04
摘要： PURPOSE:To obtain the digital processing ghost elimination device brought into practical use through the reduction of a circuit scale. CONSTITUTION:An output of a subtractor 29 is given to equalization units connected in cascade. Each equalization unit delays an inputted signal by a variable delay circuit in a delay quantity in response to the ghost delay time and gives the result to a next stage equalization unit. The output of a transversal filter of each equalization unit is added to an output from other equalization unit and the output of an adder of a first stage is given to the subtractor 29 as a ghost cancel signal. The subtractor 29 subtracts the ghost cancel signal from a television signal to output an output from which ghost is eliminated. Thus, the ghost in the delay time of a wide range is eliminated with less number of taps.

6. 发明专利

JPH04129479A WAVEFORM EQUALIZER 失效
公开(公告)号：JPH04129479A
公开(公告)日：1992-04-30
申请号：JP25259490
申请日：1990-09-20
申请人： TOSHIBA CORP
发明人： IGA HIROYUKI
IPC分类号： H04N5/21
摘要： PURPOSE:To relieve the load of the hardware and to decrease the time required for ghost elimination by obtaining a tap coefficient matrix from an autocorrelation matrix of an input reference waveform and correlation matrix between a reference waveform and an input reference waveform and applying correlation calculation of input output reference waveforms so as to correct the tap coefficient sequentially. CONSTITUTION:A 1st arithmetic means obtains an autocorrelation matrix of an input reference waveform, a 2nd arithmetic means obtains a correlation matrix of an input reference waveform and a reference waveform, and a 3rd arithmetic means obtains a tap coefficient from the result of arithmetic operations. The major part of the arithmetic operation is implemented by a product sum accumulator 14. Then the tap coefficient obtained by the 3rd arithmetic means is given to a transversal filter 3, in which the input waveform is waveform-equalized. Then a 4th arithmetic means calculates the correlation of the input and output reference waveforms to correct the tap coefficient obtained by the 3rd arithmetic means sequentially. Thus, the time required for eliminating ghost is reduced without increasing the scale of the hardware.

7. 发明专利

JPH03190379A GHOST ELIMINATION DEVICE 失效
公开(公告)号：JPH03190379A
公开(公告)日：1991-08-20
申请号：JP32825189
申请日：1989-12-20
申请人： TOSHIBA CORP
发明人： MATSUI NORIKO , IGA HIROYUKI
IPC分类号： H04N5/21
摘要： PURPOSE:To reduce the converging time by taking a difference with a ghost elimination reference signal (GCR) fetched at 4 preceding field from a current field for each field when the GCR is fetched and forming one field type for a minimum tap gain correction period. CONSTITUTION:A current fetch waveform is always stored in an area M1 and a waveform of 4 preceding field is stored in an area M5 by sending the content of a memory sequentially every time a GCR is fetched. Thus, the calculation of a GCR(SGCR) has an advantage that it is implemented fixedly by using the areas M1, M5. However, it takes time for a job to transfer the content of the memory sequentially before the GCR is fetched. Then a method of storing a signal in an area in which the oldest GCR of 4 preceding field to the current field is taken every time the GCR is fetched. Thus, the transfer from the memory area to the other memory area is omitted and the time is reduced.

8. 发明专利

JPH03114366A GHOST ELIMINATION DEVICE 失效
公开(公告)号：JPH03114366A
公开(公告)日：1991-05-15
申请号：JP25045889
申请日：1989-09-28
申请人： TOSHIBA CORP
发明人： MATSUE HIROSHI , IGA HIROYUKI
IPC分类号： H04N5/21
摘要： PURPOSE:To prevent cost-up of the device due to fetch of a GCR signal by obtaining a final GCR signal based on a prescribed arithmetic processing algorithm after the GCR signal by 8 fields is fetched from 18H. CONSTITUTION:The device consist of an input terminal 11, an A/D converter circuit 12, a clock generating circuit 4, a transversal filter (TF) 15, an output terminal 16, a microprocessor 17, a ROM 18, a work RAM 19, an output waveform memory 20, a fetch control circuit 21 and a 18H detection circuit 31. Then after a reference signal (GCR signal) to eliminate a ghost signal included in the video signal by 8 fields starting from the 18th horizontal scanning line (18H) of an odd number field, the final GCR signal is obtained based on a prescribed arithmetic algorithm. Thus, the expensive device due to fetch of the GCR signal is eliminated.

9. 发明专利

JPH02241107A WAVEFORM EQUALIZER 失效
公开(公告)号：JPH02241107A
公开(公告)日：1990-09-25
申请号：JP6304589
申请日：1989-03-14
申请人： TOSHIBA CORP
发明人： MOROMOTO HIROYUKI , IGA HIROYUKI
IPC分类号： H03H15/00 , H04B3/04
摘要： PURPOSE:To eliminate residual ghost and to attain stable ghost elimination by using a vertical synchronizing signal as a reference signal in the initial state at application of power or channel changeover and switching an exclusive signal or the vertical synchronizing signal after the convergence with ghost elimination. CONSTITUTION:A transversal filter TF consists of a delay circuit 13 comprising a unit time delay serial element group having a tap, a multiplier group 14, an adder 15 and a tap coefficient memory 16. In this case, ghost is eliminated by using the vertical synchronizing signal as a reference signal at the initial state of equalization and when the equalization at the initial state is converged, a GCR(Ghost Cancellor Reference) signal is detected and when a GCR signal exists, the reference signal is switched into the equalization processing by the GCR signal to continue the equalization processing. Thus, a long ghost is surely eliminated and ghost is eliminated at application of power or the start of channel changeover or the like.

10. 发明专利

JPH02165714A DELAY LINE INTEGRATED CIRCUIT WITH TAP AND ITS CASCADE CONNECTION CIRCUIT 失效
公开(公告)号：JPH02165714A
公开(公告)日：1990-06-26
申请号：JP32153488
申请日：1988-12-19
申请人： TOSHIBA CORP
发明人： ISHII AKIRA , IGA HIROYUKI
IPC分类号： H04N5/21 , H03H15/00 , H04B3/04
摘要： PURPOSE:To reduce the number of terminals and to enable the setting position of a delay line to be selected corresponding to a system by providing a variable delay means which performs a delay processing only by a delay quantity set by an external signal at either the path of a common input signal supplied to each unit circuit or the signal path of an addition signal. CONSTITUTION:In the case of performing the cascade connection of integrated circuits TF1-TFl, the common input signal or a sequential addition signal to each unit circuit can be delayed by a prescribed quantity required for individual integrated circuit by the variable delay means 13, and no output terminal of the common signal to the integrated circuit at the succeeding stage is required. Also, since the variable delay means 13 can set arbitrary delay time for each integrated circuit individually, it is possible to omit the delay line at a position where no ghost occurs by applying the subject circuit on the system in which the delay line is required only at the position where the ghost occurs like a ghost canceller.

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