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1. 发明专利

JPS61251285A DESCRAMBLE DEVICE 失效
公开(公告)号：JPS61251285A
公开(公告)日：1986-11-08
申请号：JP9093185
申请日：1985-04-30
申请人： TOSHIBA CORP , TOSHIBA AUDIO VIDEO ENG , JAPAN BROADCASTING CORP
发明人： KUDO YUKINORI , NAKAGAWA MASAKI , KOMATSU SUSUMU , MORII YUTAKA , SOEJIMA MASAHIRO , YAMAZAKI NOBORU
IPC分类号： H04K1/00 , G06F21/10 , H04N7/167 , H04N7/169
摘要： PURPOSE:To correspond to both modes of NTSC, and scramble without using a delay correcting circuit of analog by operating a whole of the system as a PLL system using a digital synchronous signal in a scramble mode and as the PLL system using a burst signal in the NTSC mode. CONSTITUTION:PLL arithmetic circuits 120, 120 used in the descramble device have PLL error arithmetic circuits 121, 122 correspondingly to a scramble mode, an NTSC mode respectively and comprises a change over circuit 123 for changing over and outputting in accordance with a mode outputs of the error arithmetic circuits 121, 122 and a loop filter 124. Respectively calculated error signals Es, En are supplied together to the change-over circuit 123. The change-over circuit 123 selects Es during the scramble mode in accordance with a mode change over signal 53, and En during the NTSC mode, respectively and supplies as an output signal 125 to the loop filter 124. The loop filter 124 smoothes the inputted error signal 125 and supplies as a phase error signal 15 to a D/A converting circuit.

2. 发明专利

JPS61234139A PHASE LOCKED LOOP 失效
公开(公告)号：JPS61234139A
公开(公告)日：1986-10-18
申请号：JP7475085
申请日：1985-04-09
申请人： TOSHIBA CORP , JAPAN BROADCASTING CORP
发明人： MURAKAMI JUNZO , YAMAZAKI NOBORU , YOROZU MASATOSHI
IPC分类号： H04L7/033 , H04N5/12
摘要： PURPOSE:To obtain a reproducing clock which is less in phase jitters caused by noises by inserting an amplitude limiter between a phase comparator and loop filter. CONSTITUTION:When a noise component is contained in the input signal of a phase comparator 16, the output of the comparator 16 is changeable over the full range of -256/256-256/256 depending upon the scale of the noise. An amplitude limiter 6 is provided to suppress such an output which depends upon noise components and its amplitude limiting range is set to an extent which is almost equal to the amplitude changing range, -64/256-64/256, of phase error signals produceable in the output of the phase comparator 16 when no noise component exists in the input signal. Therefore, the amplitude changing range of a signal supplied to a loop filter 7 never exceeds the amplitude changing range of the original phase error signal caused by the phase error of a sampling clock, even if the noise of any instantaneous amplitude is mixed in the input signal.

3. 发明专利

JPS61234138A PHASE LOCKED LOOP 失效
公开(公告)号：JPS61234138A
公开(公告)日：1986-10-18
申请号：JP7474985
申请日：1985-04-09
申请人： TOSHIBA CORP , JAPAN BROADCASTING CORP
发明人： MURAKAMI JUNZO , YAMAZAKI NOBORU , YOROZU MASATOSHI
IPC分类号： H04L7/033 , H04L7/08 , H04N5/10 , H04N5/12
摘要： PURPOSE:To remarkably shorten the time required until phase lock is established by forcedly performing initial leading-in operations by resetting a frequency dividing circuit when an asynchronous state continuously occurs over a time period longer than a certain degree of period. CONSTITUTION:A frame pulse (FP) phase comparator circuit 4 performs phase comparison between a detected FP point and the specific point of an internal FP signal which is the output of a frequency dividing circuit 12 and outputs '0', when the difference between both points is within the range of + or -1 clock. The circuit 4 outputs '1' if the difference between both points is out of the range of + or -1 clock. A discriminating circuit 13 observes the output of the FP phase comparator circuit 4 and, when '1' is continuously observed by a previously fixed number of times (for example: 8 times), outputs '1'. A reset pulse generating circuit 14 is set to a waiting state when the output of the discriminating circuit 13 changes from '0' to '1' and generates a reset pulse 15 at the timing of first arriving detected FP point. Then a loop filter 6 and frequency dividing circuits 11 and 12 are reset to prescribed initial states.

4. 发明专利

JPH0332274B2 失效
公开(公告)号：JPH0332274B2
公开(公告)日：1991-05-10
申请号：JP21490082
申请日：1982-12-08
申请人： JAPAN BROADCASTING CORP
发明人： NINOMYA JUICHI , NISHIZAWA DAIJI , OKADA KYOTAKA , TANAKA YUTAKA , YAMAZAKI NOBORU , YOROZU MASATOSHI
IPC分类号： H04N7/01 , H04N7/015

5. 发明专利

JPS5459034A DISPLAY METHOD FOR CHARACTERS AND THE LIKE 失效
公开(公告)号：JPS5459034A
公开(公告)日：1979-05-12
申请号：JP12610877
申请日：1977-10-19
申请人： JAPAN BROADCASTING CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： OKANO HIROSUKE , IZURA YOSHIMITSU , TAKADA YUKIO , SAEKI HIROAKI , TANABE YOSHIHIRO , MIYAZAKI TAKUROU , MORII YUTAKA , YOSHIDA MAKOTO , YAMAZAKI NOBORU
IPC分类号： G09G5/36 , G06F3/14 , G09G5/00 , G09G5/28
摘要： PURPOSE:To eliminate the notches peculiar to the digital character even with use of the refresh memory featuring a comparatively small capacity by applying so- called ''blurring'' operation based on the peripheral information. CONSTITUTION:The signals to be conveted [(a) and 21a-27a are scanning lines] are applied to terminal 11 to deliver (19) the converted signals [(b) and 21b-27b are scanning lines] via the following units: 1H period delay shift register SR12 and 13; SR14-16 to draw out specified two bits each; arithmetic circuit 17 which multiplies weight n1, n2 and n1 determined to each bit and the obtains the sum; and converter circuit 18 which delivers ''11'' in case the result of circuit 17 is larger than prescribed value n3, delivers ''00'' in case the result is smaller than prescribed value n4 and ''01'' in other cases respectively. Thus, pattern (a) is converted to pattern (b), and the information of one screen is memorized in the refresh memory to be displayed directly (A). Thus, the notches of the display character can be improved by the visual integration effect. After this, the smoothing correction is given to obtain pattern (B).

6. 发明专利

JPS61261994A RECEIVER FOR VIDEO SIGNAL 失效
公开(公告)号：JPS61261994A
公开(公告)日：1986-11-20
申请号：JP10308985
申请日：1985-05-15
申请人： SONY CORP , JAPAN BROADCASTING CORP
发明人： MATSUNAGA OSAMU , TATSUHIRA YASUSHI , YAMAZAKI NOBORU , YOROZU MASATOSHI , NINOMIYA YUICHI
IPC分类号： H04N11/08 , H04N11/24
摘要： PURPOSE:To make it possible to control an image without providing an exclusive circuit by making it possible to vary a correcting quantity that corrects the change of a gain independently and respectively in a luminance signal period and in a chrominance signal period. CONSTITUTION:A signal SMVA from an inter-frame correcting circuit is supplied to an input terminal 12. And the inputs/outputs of D-FF 13-16 are, after they are weighed respectively by coefficient apparatuses 18-22, added at an adder 23. Also, a component S16 existing at the neighbor of 16.2mHz from the adder 23 is supplied to an adder 25 through a gain controlling ROM 24 and is added with the output of the D-FF14. And the output of the adder 25 is supplied to an output terminal 27 through a bit number controlling limiter 26. At such a time, the level of the component S16 which is supplied to the adder 25 is varied based on signals SY1-SY3.

7. 发明专利

JPS61261982A HIGH DEFINITION TELEVISION RECEIVER 失效
公开(公告)号：JPS61261982A
公开(公告)日：1986-11-20
申请号：JP10309085
申请日：1985-05-15
申请人： SONY CORP , JAPAN BROADCASTING CORP
发明人： OKADA TAKAFUMI , KOBAYASHI HIROYUKI , YAMAZAKI NOBORU , MORII YUTAKA , NINOMIYA YUICHI
IPC分类号： H04N7/01 , H04N7/00 , H04N7/015 , H04N19/00 , H04N19/50
摘要： PURPOSE:To improve picture quality by displaying a non-interlaced double scanning and processing a motion adaptive interpolation which is different at a still picture part or at a moving picture part. CONSTITUTION:A double scanning conversion means which converts a received television signal of an MUSE system to the television signal of a non-interlaced double scanning system is prepared and a signal converted by the means is displayed on a color picture tube 20 as a picture. An inter-four fields interpolation means 12 and a within-field interpolation means 9 are provided at the double scanning conversion means and the inter-four fields interpolation means 12 and the within-field interpolation means 9 are controlled by the output of a means 14 which detects the motion of the picture. And at the still picture part, the picture of a scanning line which is interpolated by the output of the inter-four fields interpolation means 12 is generate and at the moving picture part, the picture of the scanning line which is interpolated by the output of the within-field interpolation means 9 is generated. Thus, a sufficient resolution power is obtained.

8. 发明专利

JPS54157441A DISPLAY UNIT 失效
公开(公告)号：JPS54157441A
公开(公告)日：1979-12-12
申请号：JP6638978
申请日：1978-06-01
申请人： JAPAN BROADCASTING CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： TANABE YOSHIHIRO , MIYAZAKI TAKUROU , MORII YUTAKA , YOSHIDA MAKOTO , YAMAZAKI NOBORU , OKANO HIROSUKE , IZURA YOSHIMITSU , TAKADA YUKIO , SAEKI HIROAKI
IPC分类号： G06F3/14
摘要： PURPOSE:To reduce the flicker and thus to ensure a smooth and easy-to-see diaplay of characters by recording the information on two field display memories in correspondence to the vertical odd and even dots of one character and then reading out the information in the same timing for display. CONSTITUTION:The information of the characters, symbols and the like registered to floppy disk 4 is selected through operation board 1 and then memorized in 1- frame memory 7 through control circuit 2 and 3. The information is memorized in dot structure in the memory region of memory 7 corresponding to the display region of monitor TV9. And the vertical odd dots of one character and the even dots are transferred and memorized into field display memory 11 and 12 each with control of address generator circuit 10. At the same time, the contents of memory 11 and 12 are read out in the same timing for multiplication and then displayed alternately at TV9. In this way, the flicker is reduced to ensure a smooth display of characters.

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