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1. 发明申请

WO2006009461A8 AN ORGANIC FERROELECTRIC OR ELECTRET MEMORY CIRCUIT AND A METHOD FOR MAKING SAME 审中-公开
标题翻译：一种有机铁电或电磁存储器电路及其制造方法
公开(公告)号：WO2006009461A8
公开(公告)日：2006-04-20
申请号：PCT/NO2005000267
申请日：2005-07-18
申请人： THIN FILM ELECTRONICS ASA , LILJEDAHL RICKARD , SANDBERG MATS , GUSTAFSSON GOERAN , GUDESEN HANS GUDE
发明人： LILJEDAHL RICKARD , SANDBERG MATS , GUSTAFSSON GOERAN , GUDESEN HANS GUDE
IPC分类号： G11C20060101 , G11C11/22 , H01L49/02
CPC分类号： G11C11/22 , B82Y10/00
摘要： In an organic electronic circuit (C), particularly a memory circuit with an organic ferroelectric or electret material (2) the active material comprises fluorine atoms and consists of various organic materials. The active material is located between a first electrode and a second electrode. A cell with a capacitor-like structure is defined in the active material and can be accessed for an addressing operation via a first and a second electrode. At least one of these electrodes (1 a, 1 b) comprises a layer of chemically modified gold. In a passive matrix-addressable electronic device, particularly a ferroelectric or electret memory device, circuits (C) of this kind with the active material as a ferroelectric or electret memory material form the elements of a matrix-addressable array and define the memory cells provided between first and second set of addressing electrodes. At least the electrodes of at least one of the sets then comprise at least a layer of gold. A method in the fabrication of the organic electronic circuit (C) the method comprises steps for depositing a layer of gold as at least one layer of at least one electrode and treating an exposed surface of this layer chemically, whereafter the layer of active material can be deposited on the top of the processed surface of this electrode.
摘要翻译：在有机电子电路（C）中，特别是具有有机铁电或驻极体材料（2）的存储电路中，活性材料包含氟原子并且由各种有机材料组成。活性材料位于第一电极和第二电极之间。具有电容器状结构的电池被定义在活性材料中，并且可以通过第一和第二电极访问寻址操作。这些电极（1a，1b）中的至少一个包括化学修饰的金层。在无源矩阵可寻址电子器件，特别是铁电或驻极体存储器器件中，这种具有作为铁电或驻极体存储材料的活性材料的电路（C）形成矩阵可寻址阵列的元件并且限定所提供的存储器单元在第一和第二组寻址电极之间。然后至少一个组的至少电极包括至少一层金。一种制造有机电子电路（C）的方法，该方法包括以下步骤：沉积金层作为至少一个电极的至少一个层，并化学处理该层的暴露表面，随后该活性材料层可以沉积在该电极的处理过的表面的顶部。

2. 发明申请

WO2006009463A8 ELECTRICAL VIA CONNECTION AND ASSOCIATED CONTACT MEANS AS WELL AS A METHOD FOR THEIR MANUFACTURE 审中-公开
标题翻译：电气通过连接和相关的接触方式作为其制造方法
公开(公告)号：WO2006009463A8
公开(公告)日：2006-04-20
申请号：PCT/NO2005000269
申请日：2005-07-18
申请人： THIN FILM ELECTRONICS ASA , LILJEDAHL RICKARD , GUSTAFSSON GOERAN
发明人： LILJEDAHL RICKARD , GUSTAFSSON GOERAN
IPC分类号： G11C20060101 , H01L51/00 , H01L23/538 , G11C11/22 , H01L21/28 , H01L51/20
CPC分类号： H01L51/0021
摘要： An electrical via connection and associated contact means in an organic electronic circuit, particularly a memory circuit is provided interfacing a layer of active organic dielectric material comprising various organic compounds. The via connection is provided in a via opening extending through the active dielectic material and connected with first and second electrical contact means on either side thereof. The second contact means comprises a first layer of chemically inert and non-reactive conducting material deposited directly on active dielectric layer, and a conducting material provided as a second layer over the first layer and in via opening down to the first contact means, creating a via connection through the active dielectric layer and connecting the first and the second contact means. In a method for manufacturing an electric via connection and associated contact means of this kind, a first layer in a second contact means is deposited on the active dielectric layer. The first layer consists of a chemically inert and non-reactive conducting material. A via opening is formed through the active dielectric layer of the second contact means consisting of a conducting material is deposited over the first layer and in the via opening to establish the desired via connection therethrough.
摘要翻译：提供有机电子电路中的电通孔连接和相关接触装置，特别是存储电路，其连接包含各种有机化合物的活性有机介电材料层。通孔连接设置在延伸穿过有源介电材料的通孔中，并与其两侧的第一和第二电接触装置连接。第二接触装置包括直接沉积在有源电介质层上的化学惰性和非反应性导电材料的第一层，以及在第一层上提供的第二层和通向第一接触装置的通孔的导电材料，通过有源电介质层的连接并连接第一和第二接触装置。在用于制造电通孔连接和这种相关联的接触装置的方法中，第二接触装置中的第一层沉积在有源电介质层上。第一层由化学惰性和非反应性导电材料组成。通过第二接触装置的有源电介质层形成通孔，该电介质层由导电材料构成，沉积在第一层上并在通孔开口中以建立所需的通孔连接。

3. 发明申请

WO0225665A3 NON-VOLATILE PASSIVE MATRIX AND METHOD FOR READOUT OF THE SAME 审中-公开
标题翻译：非易失性被动矩阵及其读取方法
公开(公告)号：WO0225665A3
公开(公告)日：2002-05-16
申请号：PCT/NO0100348
申请日：2001-08-24
申请人： THIN FILM ELECTRONICS ASA , THOMPSON MICHAEL , WOMACK RICHARD , GUSTAFSSON GOERAN , CARLSSON JOHAN
发明人： THOMPSON MICHAEL , WOMACK RICHARD , GUSTAFSSON GOERAN , CARLSSON JOHAN
IPC分类号： G11C7/06 , G11C7/10 , G11C11/22 , H01L21/8246 , H01L27/105 , G11C8/12 , G11C8/14
CPC分类号： G11C7/1006 , G11C7/06 , G11C11/22
摘要： In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis between first and second sets (14; 15) of addressing electrodes constituting word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) each segment sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit lines (BL) of a segment (S) with a sensing means (26) enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logicalvalue. In a readout method,a word line (WL) of a segment (S) is activated by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of a segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26).
摘要翻译：在非易失性无源矩阵存储器件（10）中，包括电可极化介质存储器材料（12），其在构成字线（WL）的寻址电极和位线（BL）的第一组和第二组（14; 15）之间呈现迟滞，存储设备。存储单元（13）在字线（WL）和位线（BL）之间的重叠处被限定在存储器材料（12）中。字线（WL）被划分成段（S），每个段共享并由相邻的位线（BL）定义。提供装置（25）用于将段（S）的每个位线（BL）与感测装置（26）连接，使得能够同时连接字线段（15）的所有存储单元（13），以经由位读出线（BL）。每个感测装置（26）感测位线（BL）中的电荷流，以便确定存储的逻辑值。在读出方法中，通过在读周期的至少一部分期间将其电位设置为存储单元（13）的开关电压Vs来激活段（S）的字线（WL），同时保持位线（S）的零电位（BL），在该期间，存储在各个存储单元（13）中的逻辑值由读取周期由感测装置（26）感测。

4. 发明申请

WO9963527A3 DATA STORAGE AND PROCESSING APPARATUS, AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：数据存储和处理装置及其制造方法
公开(公告)号：WO9963527A3
公开(公告)日：2000-02-17
申请号：PCT/NO9900181
申请日：1999-06-02
申请人： THIN FILM ELECTRONICS ASA , GUDESEN HANS GUDE , NORDAL PER ERIK , LEISTAD GEIRR I , CARLSSON JOHAN , GUSTAFSSON GOERAN
发明人： GUDESEN HANS GUDE , NORDAL PER-ERIK , LEISTAD GEIRR I , CARLSSON JOHAN , GUSTAFSSON GOERAN
IPC分类号： G06F1/16 , G11C17/00 , H01L21/768 , H01L21/822 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00 , H01L27/10 , H01L51/40
CPC分类号： H01L51/0001 , G11C5/02 , G11C17/06 , H01L21/2026 , H01L21/768 , H01L21/76888 , H01L21/76894 , H01L21/8221 , H01L27/0688 , H01L27/1021 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/11 , H01L27/11502 , H01L51/0024 , H01L2924/0002 , H01L2924/00
摘要： A data storage and processing apparatus comprising ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules on a substrate. The memory and/or processing modules are provided as a single main layer or multiple main layers on the top of the substrate. The apparatus comprises active components in the form of transistors and/or diodes for operating the apparatus. In one set of embodiments at least some and at most all the transistors and/or diodes for operating the apparatus are provided on or in the substrate. In another set of embodiments at least some and at most all of the layers on the top of the substrate comprise low-temperature compatible organic materials and/or low temperature compatible processed inorganic films, even without requiring transistors and/or diodes to be provided on or in the substrate. In a method for fabricating a data storage and processing apparatus of this kind, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps. The deposition and processing of the layers take place under thermal conditions that avoid subjecting an already deposited and processed underlying layer or layers to static or dynamic temperatures exceeding given stability limits, particularly in regard of organic materials.
摘要翻译：一种包括ROM和/或WORM和/或REWRITEABLE存储器模块和/或衬底上的处理模块的数据存储和处理设备。存储器和/或处理模块作为单个主层或多个主层提供在衬底的顶部上。该装置包括用于操作该装置的晶体管和/或二极管形式的有源部件。在一组实施例中，用于操作设备的至少一些和至多所有晶体管和/或二极管用于提供在衬底上或衬底中。在另一组实施方案中，衬底顶部上的至少一些和至多所有层包括低温相容的有机材料和/或低温相容的经处理的无机膜，即使不需要在二极管上提供晶体管和/或二极管或在基材中。在这种用于制造这种数据存储和处理装置的方法中，通过以连续的步骤沉积层来在存储器和/或处理模块上提供存储器和/或处理模块。层的沉积和加工在热条件下进行，避免了将已经沉积和加工的下层或多层经受超过给定稳定极限的静态或动态温度，特别是在有机材料方面。

5. 发明申请

WO0065653A9 A METHOD IN THE FABRICATION OF ORGANIC THIN-FILM SEMICONDUCTING DEVICES 审中-公开
标题翻译：有机薄膜半导体器件的制造方法
公开(公告)号：WO0065653A9
公开(公告)日：2004-08-05
申请号：PCT/NO0000127
申请日：2000-04-14
申请人： THIN FILM ELECTRONICS ASA , ROMAN LUCIMARA STOLZ , INGANAES OLLE , HAGEL OLLE , BERGGREN MAGNUS , GUSTAFSSON GOERAN , CARLSSON JOHAN
发明人： ROMAN LUCIMARA STOLZ , INGANAES OLLE , HAGEL OLLE , BERGGREN MAGNUS , GUSTAFSSON GOERAN , CARLSSON JOHAN
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L29/786 , H01L29/861 , H01L51/00 , H01L51/05 , H01L51/10 , H01L51/30 , H01L51/40 , H01L27/01 , H01L49/02
CPC分类号： H01L51/424 , H01L51/0036 , H01L51/0037 , H01L51/0038 , Y02E10/549
摘要： In a method in the fabrication of an organic thin-film semiconducting device comprising an electrode arrangement with electrodes contacting a semiconducting organic material, an anode in the electrode arrangement is made as a two-layer structure, where the first layer is a conducting or semiconducting material or a combination thereof deposited on a substrate and a second layer is a conducting polymer with a work function higher than that of the material in the first layer. A third layer consisting of semiconducting organic material and forming the active material of the device is deposited on the top of the anode, and the cathode made of a fourth layer of a metal deposited on a third layer. In a preferred embodiment a low work function metal is used in the first layer, a doped conjugated polymer such as PEDOT-PSS in the second layer, while the cathode may be formed of the same metal as used in the first layer. Use in the manufacturing of the electrode arrangement in an organic thin-film diode or in a transistor structure.
摘要翻译：在制造有机薄膜半导体器件的方法中，包括具有与半导体有机材料接触的电极的电极装置，电极装置中的阳极被制成两层结构，其中第一层是导电或半导体沉积在基底和第二层上的材料或其组合是导电聚合物，其功函数高于第一层中的材料。由半导体有机材料构成并形成器件的活性材料的第三层沉积在阳极的顶部，阴极由沉积在第三层上的第四层金属制成。在优选实施例中，在第一层中使用低功函数金属，在第二层中使用诸如PEDOT-PSS的掺杂共轭聚合物，而阴极可以由与第一层中使用的相同的金属形成。用于制造有机薄膜二极管或晶体管结构中的电极布置。

6. 发明专利

JP2007087579A Address specification of memory matrix 审中-公开
标题翻译：存储器矩阵的地址规范
公开(公告)号：JP2007087579A
公开(公告)日：2007-04-05
申请号：JP2006287634
申请日：2006-10-23
申请人： Thin Film Electronics Asa , シンフイルムエレクトロニクスエイエスエイ
发明人： THOMPSON MICHAEL , NORDAL PER-ERIK , GUSTAFSSON GOERAN , CARLSSON JOHAN , GUDESEN HANS GUDE
IPC分类号： G02F1/133 , G11C11/22 , G09G3/20 , G09G3/36 , G11C7/06 , G11C7/10 , G11C8/18 , H01L21/8246 , H01L27/105
CPC分类号： G11C11/22 , G09G3/20 , G09G3/3629 , G09G2300/06 , G09G2310/0251 , G09G2320/0209 , G11C7/06 , G11C7/1006 , G11C8/18
摘要： PROBLEM TO BE SOLVED: To provide a voltage to time protocol for driving (x) and (y) passive matrix address specification line in a nonvolatile memory indicating hysteresis curve of a ferroelectric object so that disturbance of memory cells being not selected is made the minimum. SOLUTION: Potentials on all word lines and bit lines are controlled temporally conforming to a protocol by controlling so that potentials on a selected word line and a bit line are approximated or made coincident to one out of the predetermined potential levels of (n) pieces, so as to connect to bit lines (single or multiple) and a circuit for detecting electric charges flowing between the bit line and a cell during the predetermined period of timing sequence given by the protocol, latching successively word lines to potentials selected from potentials of n word pieces, meanwhile, latching successively bit lines to potentials selected from potentials of (n) bit pieces. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了在指示铁电体的磁滞曲线的非易失性存储器中提供用于驱动（x）和（y）无源矩阵地址指定线的时间协议电压，使得未选择的存储器单元的干扰为做到最小。解决方案：所有字线和位线上的电位通过控制在时间上受控于协议的控制，使得所选字线和位线上的电位近似于或与（n ），以便在协议给定的定时序列的预定时段期间连接到位线（单个或多个）和用于检测在位线和单元之间流动的电荷的电路，将连续的字线锁定到从同时，将（n）位的电位中选择的电位连续的位线锁存在n 字的电位上。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2012178566A Method of fabricating ferroelectric memory device 审中-公开
标题翻译：制造电磁存储器件的方法
公开(公告)号：JP2012178566A
公开(公告)日：2012-09-13
申请号：JP2012054625
申请日：2012-03-12
申请人： Thin Film Electronics Asa , シンフイルムエレクトロニクスエイエスエイ
发明人： PETER DYREKLEV , LEISTAD GEIRR I , GUSTAFSSON GOERAN
IPC分类号： H01L27/105 , B41M1/30 , G11C20060101 , G11C11/22 , H01L21/8246 , H01L27/28 , H01L51/05 , H05K3/12
CPC分类号： H01L27/11507 , G11C11/22 , H01L27/11502 , H05K3/12
摘要： PROBLEM TO BE SOLVED: To provide an easy and inexpensive method of making a rewritable non-volatile memory device which can be easily incorporated in a tag, label or package printing process or the packaging process itself.SOLUTION: The fabrication method may comprise successive steps of a) printing a first electrode layer with a first printing ink onto an insulating substrate using first printing means, thereby forming a first set of electrodes, b) printing a patterned or unpatterned layer of memory material with a second printing ink onto the first electrode layer using second printing means, and c) printing a second electrode layer with a third printing ink onto the memory layer using third printing means, thereby forming the second set of electrodes. The method may be implemented by various printing processes either separately or in combination.
摘要翻译：要解决的问题：提供一种易于且廉价的制造可重写的非易失性存储器件的方法，其可以容易地结合在标签，标签或封装印刷过程或包装过程本身中。解决方案：制造方法可以包括以下连续步骤：a）使用第一印刷装置将具有第一印刷油墨的第一电极层印刷到绝缘基板上，从而形成第一组电极，b）印刷图案化或未图案化的层使用第二印刷装置将具有第二印刷油墨的第二印刷油墨注入到第一电极层上，以及c）使用第三印刷装置将具有第三印刷油墨的第二电极层印刷到存储层上，由此形成第二组电极。该方法可以通过各种印刷方法单独地或组合地实现。版权所有（C）2012，JPO＆INPIT

8. 发明专利

AT525706T 未知
公开(公告)号：AT525706T
公开(公告)日：2011-10-15
申请号：AT06747668
申请日：2006-06-08
申请人： THIN FILM ELECTRONICS ASA
发明人： BROEMS PER , KARLSSON CHRISTER , LEISTAD GEIRR , GUDESEN HANS GUDE , HAMBERG PER , BJOERKLID STAFFAN , CARLSSON JOHAN , GUSTAFSSON GOERAN
IPC分类号： G06K19/067 , G06K20060101 , G06K1/12 , G06K7/00 , G06K7/06 , G06K7/08 , G06K19/06 , G11B9/00 , G11C11/22
摘要： In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

9. 发明专利

AT523881T 未知
公开(公告)号：AT523881T
公开(公告)日：2011-09-15
申请号：AT06747667
申请日：2006-06-08
申请人： THIN FILM ELECTRONICS ASA
发明人： DYREKLEV PETER , LEISTAD GEIRR , GUSTAFSSON GOERAN
IPC分类号： G11C11/22 , G11C20060101 , H01L21/8246 , H01L51/40 , H05K3/12
摘要： In a method in the fabrication of a ferroelectric memory device comprising a memory layer sandwiched between first and second electrode sets, the memory layer as well as both electrode sets are each realized in the memory device by a suitable printing process.

10. 发明专利

AT290711T 未知
公开(公告)号：AT290711T
公开(公告)日：2005-03-15
申请号：AT01985301
申请日：2001-08-24
申请人： THIN FILM ELECTRONICS ASA
发明人： THOMPSON MICHAEL , WOMACK RICHARD , GUSTAFSSON GOERAN , CARLSSON JOHAN
IPC分类号： G11C7/06 , G11C7/10 , G11C11/22 , H01L21/8246 , H01L27/105 , G11C5/00
摘要： In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, first and second sets (14; 15) of addressing electrodes constitute word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) with each segments sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit line (BL) of a segment (S) with a sensing means (26), thus enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL) of the segment (S). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logical value. In a readout method a word line (WL) of a segment (S) is activated by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of the segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26). -Use in a volumetric data storage apparatus.

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