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    • 1. 发明申请
    • NON-VOLATILE PASSIVE MATRIX AND METHOD FOR READOUT OF THE SAME
    • 非易失性被动矩阵及其读取方法
    • WO0225665A3
    • 2002-05-16
    • PCT/NO0100348
    • 2001-08-24
    • THIN FILM ELECTRONICS ASATHOMPSON MICHAELWOMACK RICHARDGUSTAFSSON GOERANCARLSSON JOHAN
    • THOMPSON MICHAELWOMACK RICHARDGUSTAFSSON GOERANCARLSSON JOHAN
    • G11C7/06G11C7/10G11C11/22H01L21/8246H01L27/105G11C8/12G11C8/14
    • G11C7/1006G11C7/06G11C11/22
    • In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis between first and second sets (14; 15) of addressing electrodes constituting word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) each segment sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit lines (BL) of a segment (S) with a sensing means (26) enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logicalvalue. In a readout method,a word line (WL) of a segment (S) is activated by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of a segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26).
    • 在非易失性无源矩阵存储器件(10)中,包括电可极化介质存储器材料(12),其在构成字线(WL)的寻址电极和位线(BL)的第一组和第二组(14; 15)之间呈现迟滞, 存储设备。 存储单元(13)在字线(WL)和位线(BL)之间的重叠处被限定在存储器材料(12)中。 字线(WL)被划分成段(S),每个段共享并由相邻的位线(BL)定义。 提供装置(25)用于将段(S)的每个位线(BL)与感测装置(26)连接,使得能够同时连接字线段(15)的所有存储单元(13),以经由位读出 线(BL)。 每个感测装置(26)感测位线(BL)中的电荷流,以便确定存储的逻辑值。 在读出方法中,通过在读周期的至少一部分期间将其电位设置为存储单元(13)的开关电压Vs来激活段(S)的字线(WL),同时保持位线 (S)的零电位(BL),在该期间,存储在各个存储单元(13)中的逻辑值由读取周期由感测装置(26)感测。
    • 2. 发明申请
    • SENSING DEVICE FOR A PASSIVE MATRIX MEMORY AND A READ METHOD FOR USE THEREWITH
    • 被动矩阵存储器的感测装置及其使用方法的读取方法
    • WO0217322A9
    • 2002-11-28
    • PCT/NO0100347
    • 2001-08-24
    • THIN FILM ELECTRONICS ASATHOMPSON MICHAELWOMACK RICHARD
    • THOMPSON MICHAELWOMACK RICHARD
    • G11C11/15G11C11/22G11C27/02G11C7/06
    • G11C11/22G11C27/026
    • A sensing device (10) for reading data stored in a passive matrix memory comprising memory cells in the form of ferroelectric capacitors, comprises an integrator circuit (11) for sensing the current response and means (16, 17, 18) for storing and comparing two consecutive read values, one of which is a reference value. In a read method for use with the sensing device a bit line is connected to the sensing device for sensing a charge flowing therebetween and a memory cell at the crossing of the former and an activated word line, whereafter two consecutive reads of the memory cell are performed an integrated over predetermined time periods in order to generate first and second read values which are compared for determining a logical value dependent on the sensed charge.
    • 用于读取存储在包括铁电电容器形式的存储器单元的无源矩阵存储器中的数据的传感装置(10)包括用于检测电流响应的积分器电路(11)和用于存储和比较的装置(16,17,18) 两个连续的读取值,其中之一是参考值。 在与感测装置一起使用的读取方法中,位线被连接到感测装置以用于感测在其间流动的电荷以及在前者和激活的字线的交叉处的存储器单元,此后存储器单元的两次连续读取 在预定时间周期内执行积分以产生第一读取值和第二读取值,所述第一读取值和第二读取值被比较以确定取决于感测电荷的逻辑值。
    • 3. 发明申请
    • SENSING DEVICE FOR A PASSIVE MATRIX MEMORY AND A READ METHOD FOR USE THEREWITH
    • 用于被动矩阵存储器的感测装置及其使用的读取方法
    • WO0217322A3
    • 2003-08-28
    • PCT/NO0100347
    • 2001-08-24
    • THIN FILM ELECTRONICS ASATHOMPSON MICHAELWOMACK RICHARD
    • THOMPSON MICHAELWOMACK RICHARD
    • G11C11/15G11C11/22G11C27/02G11C7/06
    • G11C11/22G11C27/026
    • A sensing device (10) for reading data stored in a passive matrix memory comprising memory cells in the form of ferroelectric capacitors, comprises an integrator circuit (11) for sensing the current response and means (16, 17, 18) for storing and comparing two consecutive read values, one of which is a reference value. In a read method for use with the sensing device a bit line is connected to the sensing device for sensing a charge flowing therebetween and a memory cell at the crossing of the former and an activated word line, whereafter two consecutive reads of the memory cell are performed an integrated over predetermined time periods in order to generate first and second read values which are compared for determining a logical value dependent on the sensed charge.
    • 一种用于读取存储在包括铁电电容器形式的存储单元的无源矩阵存储器中的数据的感测装置(10),包括用于感测电流响应的积分器电路(11)和用于存储和比较的装置(16,17,18) 两个连续的读取值,其中一个是参考值。 在与感测装置一起使用的读取方法中,位线连接到感测装置,用于感测在其间流动的电荷和在前者与激活字线交叉处的存储器单元,之后存储器单元的两个连续读取是 在预定时间周期内执行积分,以便产生第一和第二读取值,所述第一和第二读取值被比较以确定取决于感测到的电荷的逻辑值。
    • 4. 发明申请
    • READ METHOD AND SENSING DEVICE
    • 读取方法和感测装置
    • WO2006033581A9
    • 2006-06-22
    • PCT/NO2005000347
    • 2005-09-21
    • THIN FILM ELECTRONICS ASAKARLSSON CHRISTERLOEVGREN NICKLASWOMACK RICHARD
    • KARLSSON CHRISTERLOEVGREN NICKLASWOMACK RICHARD
    • G11C11/22G11C20060101G11C7/06
    • G11C11/22G11C7/062
    • In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing the method of the invention comprises a first amplifier stage (Al) with an integrator circuit (715) and connected with a second amplifier stage (A2) following the first amplifier stage and with an integrator circuit (725), and a sampling capacitor (720) connected between an output (716) of the first amplifier stage (Al) and an input (722) of the second amplifier stage (A2).
    • 在以铁电或驻极体电容器的形式存储存储单元的无源矩阵寻址铁电或驻极体存储器阵列中读取存储单元的方法中,连接到存储器单元的位线的感测装置被激活以启动电荷测量 并且注册第一充电值,之后将开关电压施加到存储单元并且登记第二充电值。 通过从第二充电值减去第一充电值获得读出值。 用于执行本发明的方法的感测装置包括具有积分器电路(715)的第一放大级(A1)并且与第一放大级之后的第二放大级(A2)和积分器电路(725)连接,以及 连接在第一放大级(A1)的输出(716)和第二放大级(A2)的输入端(722)之间的采样电容器(720)。
    • 6. 发明专利
    • AT290711T
    • 2005-03-15
    • AT01985301
    • 2001-08-24
    • THIN FILM ELECTRONICS ASA
    • THOMPSON MICHAELWOMACK RICHARDGUSTAFSSON GOERANCARLSSON JOHAN
    • G11C7/06G11C7/10G11C11/22H01L21/8246H01L27/105G11C5/00
    • In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, first and second sets (14; 15) of addressing electrodes constitute word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) with each segments sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit line (BL) of a segment (S) with a sensing means (26), thus enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL) of the segment (S). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logical value. In a readout method a word line (WL) of a segment (S) is activated by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of the segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26). -Use in a volumetric data storage apparatus.