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1. 发明申请

WO2006012127A3 MICROELECTRONIC PACKAGES AND METHODS THEREFOR 审中-公开
公开(公告)号：WO2006012127A3
公开(公告)日：2006-02-02
申请号：PCT/US2005/021968
申请日：2005-06-21
申请人： TESSERA, INC. , HABA, Belgacem , BEROZ, Masud , KANG, Teck-Gyu , KUBOTA, Yoichi , KRISHNAN, Sridhar , RILEY, John, B., III , MOHAMMED, Ilyas
发明人： HABA, Belgacem , BEROZ, Masud , KANG, Teck-Gyu , KUBOTA, Yoichi , KRISHNAN, Sridhar , RILEY, John, B., III , MOHAMMED, Ilyas
IPC分类号： H01L23/02 , H01L23/495
摘要： A microelectronic package (90) includes a microelectronic element (62) having faces, contacts and an outer perimeter, and a flexible substrate (42) overlying and spaced from a first face of the Microelectronic element (62), an outer region (86) of the flexible substrate (42) extending beyond the outer perimeter of the Microelectronic element (62). The package (90) includes a plurality of conductive posts (40a-40f) exposed at a surface of the flexible substrate (42) and being electrically interconnected with the microelectronic element (62), whereby at least one of the conductive posts (40a-40f) is disposed in the outer region (86) of the flexible substrate (42), and a compliant layer (74) disposed between the first face of the microelectronic element (62) and the flexible substrate (42), wherein the compliant layer (74) overlies the at least one of the conductive posts that is disposed in the outer region (86) of the flexible substrate (42). The package includes a support element (84) in contact with the microelectronic element (62) and the compliant layer (74), whereby the support element 84 overlies the outer region (86) of the flexible substrate (42).

2. 发明申请

WO2007075727A2 MICROELECTRONIC PACKAGES AND METHODS THEREFOR 审中-公开
标题翻译：微电子封装及其方法
公开(公告)号：WO2007075727A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/048499
申请日：2006-12-20
申请人： TESSERA, INC. , HABA, Belgacem , KANG, Teck-Gyu , MOHAMMED, Ilyas , CHAU, Ellis
发明人： HABA, Belgacem , KANG, Teck-Gyu , MOHAMMED, Ilyas , CHAU, Ellis
IPC分类号： H01L21/56 , H01L23/31 , H01L23/498
CPC分类号： H01L21/565 , G01R31/2886 , H01L21/56 , H01L23/3128 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L23/4985 , H01L23/49894 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/3011 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of making a microelectronic assembly includes providing a microelectronic package having a substrate 400, a microelectronic element 410 overlying the substrate 400 and at least two conductive elements 418 projecting from a surface 402 of the substrate 400, the at least two conductive elements 418 having surfaces 434 remote from the surface 402 of the substrate 400. The method includes compressing the at least two conductive elements 418 so that the remote surfaces 434 thereof lie in a common plane, and after the compressing step, providing an encapsulant material 430 around the at least two conductive elements 418 for supporting the microelectronic package and so that the remote surfaces 434 of the at least two conductive elements 418 remain accessible at an exterior surface of the encapsulant material 430.
摘要翻译：制造微电子组件的方法包括提供具有衬底400，覆盖衬底400的微电子元件410和从衬底400的表面402突出的至少两个导电元件418的微电子封装，该至少两个导电元件418具有远离衬底400的表面402的表面434.该方法包括压缩该至少两个导电元件418，使得其远程表面434位于公共平面内，并且在压缩步骤之后，在至少两个导电元件418周围提供用于支撑微电子封装的密封剂材料430，并且使得至少两个导电元件418的远程表面434在密封剂材料430的外表面处保持可接近。

3. 发明申请

WO2012151002A1 PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE 审中-公开
标题翻译：包装在包装上装配有电线到封装表面
公开(公告)号：WO2012151002A1
公开(公告)日：2012-11-08
申请号：PCT/US2012/028738
申请日：2012-03-12
申请人： TESSERA, INC. , SATO, Hiroaki , KANG, Teck-Gyu , HABA, Belgacem , OSBORN, Philip, R. , WANG, Wei-Shun , CHAU, Ellis , MOHAMMED, Ilyas , MASUDA, Norihito , SAKUMA, Kazuo , HASHIMOTO, Kiyoaki , INETARO, Kurosawa , KIKUCHI, Tomoyuki
发明人： SATO, Hiroaki , KANG, Teck-Gyu , HABA, Belgacem , OSBORN, Philip, R. , WANG, Wei-Shun , CHAU, Ellis , MOHAMMED, Ilyas , MASUDA, Norihito , SAKUMA, Kazuo , HASHIMOTO, Kiyoaki , INETARO, Kurosawa , KIKUCHI, Tomoyuki
IPC分类号： H01L25/10 , H01L23/498 , H01L23/538 , H01L23/31 , H01L23/495
CPC分类号： H01L24/48 , H01L21/56 , H01L23/13 , H01L23/3107 , H01L23/3128 , H01L23/4952 , H01L23/49811 , H01L23/5389 , H01L24/16 , H01L24/45 , H01L24/49 , H01L24/73 , H01L25/043 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L27/14618 , H01L27/14625 , H01L2224/05599 , H01L2224/16145 , H01L2224/16225 , H01L2224/1713 , H01L2224/17179 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45101 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/48091 , H01L2224/48106 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48245 , H01L2224/48247 , H01L2224/48455 , H01L2224/48464 , H01L2224/49105 , H01L2224/49171 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01049 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18165 , H01L2924/19107 , H01L2924/00 , H01L2924/00012
摘要： A microelectronic assembly (210) includes a substrate (212) having a first surface (214) and a second surface (216) remote from the first surface (214). A microelectronic element (222) overlies the first surface (214) and first electrically conductive elements (228) are exposed at one of the first surface (214) and the second surface (222). Some of the first conductive elements (228) are electrically connected to the microelectronic element (222). Wire bonds (232) have bases (234) joined to the conductive elements (228) and end surfaces (238) remote from the substrate (212) and the bases (234), each wire bond (232) defining an edge surface (237) extending between the base (234) and the end surface (238). An encapsulation layer (242) extends from the first surface (214) and fills spaces between the wire bonds (232) such that the wire bonds (232) are separated by the encapsulation layer (242). Unencapsulated portions of the wire bonds (232) are defined by at least portions of the end surfaces (238) of the wire bonds that are uncovered by the encapsulation layer (242).
摘要翻译：微电子组件（210）包括具有远离第一表面（214）的第一表面（214）和第二表面（216）的基底（212）。微电子元件（222）覆盖在第一表面（214）上，并且第一导电元件（228）在第一表面（214）和第二表面（222）之一处露出。第一导电元件（228）中的一些电连接到微电子元件（222）。线接合件（232）具有接合到导电元件（228）的基底（234）和远离基底（212）和基底（234）的端面（238），每个线接合（232）限定边缘表面（237））在所述基座（234）和所述端面（238）之间延伸。封装层（242）从第一表面（214）延伸并填充引线键合（232）之间的空间，使得引线键合（232）由封装层（242）分离。引线键合（232）的未封装部分由未被封装层（242）覆盖的引线接合的至少部分（238）限定。

4. 发明申请

WO2012145370A1 MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES 审中-公开
标题翻译：多芯片模块，带有堆叠式倒装连接芯片
公开(公告)号：WO2012145370A1
公开(公告)日：2012-10-26
申请号：PCT/US2012/034034
申请日：2012-04-18
申请人： TESSERA, INC. , HABA, Belgacem , MOHAMMED, Ilyas , SAVALIA, Piyush
发明人： HABA, Belgacem , MOHAMMED, Ilyas , SAVALIA, Piyush
IPC分类号： H01L25/065 , H01L25/18 , H01L23/367 , H01L23/13
CPC分类号： H01L25/18 , H01L23/02 , H01L23/13 , H01L23/367 , H01L23/3675 , H01L23/49827 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48106 , H01L2224/48227 , H01L2224/48235 , H01L2224/48465 , H01L2224/73203 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/07811 , H01L2924/09701 , H01L2924/1431 , H01L2924/1434 , H01L2924/15159 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/20645 , H05K3/303 , H05K2201/10159 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic assembly 10 can include a substrate 20 having first and second surfaces 21, 22, at least two logic chips 30 overlying the first surface, and a memory chip 40 having a front surface 45 with contacts 44 thereon, the front surface of the memory chip confronting a rear surface 36 of each logic chip. Signal contacts 34 of each logic chip 30 can be directly electrically connected to signal contacts 34 of the other logic chips 30 through conductive structure 62 of the substrate 20 for transfer of signals between the logic chips. The logic chips 30 can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts 44 of the memory chip 40 can be directly electrically connected to the signal contacts 34 of at least one of the logic chips 30 through the conductive structure 62.
摘要翻译：微电子组件10可以包括具有第一表面21和第二表面22的衬底20，覆盖第一表面的至少两个逻辑芯片30以及存储芯片40，其具有在其上的触点44的前表面45，存储器的前表面芯片面对每个逻辑芯片的后表面36。每个逻辑芯片30的信号触点34可以通过衬底20的导电结构62直接电连接到其它逻辑芯片30的信号触点34，用于在逻辑芯片之间传输信号。逻辑芯片30可以适于同时执行一个进程的给定线程的一组指令。存储芯片40的触点44可以通过导电结构62直接电连接到至少一个逻辑芯片30的信号触点34。

5. 发明申请

WO2012079013A1 HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS 审中-公开
标题翻译：高密度三维集成电容器
公开(公告)号：WO2012079013A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/064219
申请日：2011-12-09
申请人： TESSERA, INC. , OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , SAVALIA, Piyush
发明人： OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , SAVALIA, Piyush
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48 , H01L23/64
CPC分类号： H01L28/91 , H01L23/481 , H01L28/60 , H01L2223/6622 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A component (10) includes a substrate (20) and a capacitor (40). The substrate (20) can have first and second surfaces (21, 22) and an opening (30) extending from the first surface. The capacitor (40) can include first, second, third, and fourth conductive plates (61, 62, 71, 72), each plate extending along an inner surface (31) of the opening (30). The capacitor (40) can include first and second electrodes (163, 164) exposed at first and second spaced apart locations, and third and fourth electrodes (173, 174) exposed at third and fourth spaced apart locations. The third plate (71) can overlie the first plate (61) and can be separated therefrom by a first dielectric layer (81). The second plate (62) can overlie the third plate (71) and can be separated therefrom by a second dielectric layer (82). The fourth plate (72) can overlie the second plate (62) and can be separated therefrom by a third dielectric layer (83).
摘要翻译：组件（10）包括衬底（20）和电容器（40）。衬底（20）可以具有从第一表面延伸的第一和第二表面（21,22）和开口（30）。电容器（40）可以包括第一，第二，第三和第四导电板（61,62,71,72），每个板沿着开口（30）的内表面（31）延伸。电容器（40）可以包括在第一和第二间隔开的位置处暴露的第一和第二电极（163,164），以及在第三和第四间隔开的位置暴露的第三和第四电极（173,174）。第三板（71）可以覆盖第一板（61），并且可以通过第一介电层（81）与第一板（61）分离。第二板（62）可以覆盖第三板（71），并且可以通过第二介电层（82）与第三板（71）分离。第四板（72）可以覆盖第二板（62），并且可以通过第三介电层（83）与第二板（72）分离。

6. 发明申请

WO2012037220A1 MULTI-FUNCTION AND SHIELDED 3D INTERCONNECTS 审中-公开
标题翻译：多功能和屏蔽三维互联
公开(公告)号：WO2012037220A1
公开(公告)日：2012-03-22
申请号：PCT/US2011/051556
申请日：2011-09-14
申请人： TESSERA, INC. , OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , MITCHELL, Craig , SAVALIA, Piyush
发明人： OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , MITCHELL, Craig , SAVALIA, Piyush
IPC分类号： H01L23/48 , H01L23/498
CPC分类号： H01L23/49827 , H01L21/6835 , H01L23/481 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2221/68327 , H01L2221/6834 , H01L2223/6622 , H01L2224/05009 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/0557 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A microelectronic unit 10 includes a semiconductor element 20 consisting essentially of semiconductor material and having a front surface 21, a rear surface 22, a plurality of active semiconductor devices 23a, 23b adjacent the front surface 21, a plurality of conductive pads 50 exposed at the front surface 21, and an opening 30 extending through the semiconductor element 20. At least one of the conductive pads 50 can at least partially overlie the opening 30 and can be electrically connected with at least one of the active semiconductor devices 23a, 23b. The microelectronic unit 10 can also include a first conductive element 60 exposed at the rear surface 22 for connection with an external component, the first conductive element 60 extending through the opening 30 and electrically connected with the at least one conductive pad 50, and a second conductive element 40 extending through the opening 30 and insulated from the first conductive element 60. The at least one conductive pad 50 can overlie a peripheral edge 41 of the second conductive element 40.
摘要翻译：微电子单元10包括基本上由半导体材料组成并具有前表面21，后表面22，与前表面21相邻的多个有源半导体器件23a，23b的半导体元件20，在该表面21处暴露的多个导电焊盘50 前表面21和延伸穿过半导体元件20的开口30.至少一个导电焊盘50可以至少部分地覆盖开口30并且可以与有源半导体器件23a，23b中的至少一个电连接。微电子单元10还可以包括暴露在后表面22处用于与外部部件连接的第一导电元件60，第一导电元件60延伸穿过开口30并与至少一个导电焊盘50电连接，导电元件40延伸穿过开口30并与第一导电元件60绝缘。至少一个导电焊盘50可以覆盖在第二导电元件40的周边边缘41上。

7. 发明申请

WO2012011932A1 METHODS OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM 审中-公开
标题翻译：使用微粉碎颗粒流形成半导体元件的方法
公开(公告)号：WO2012011932A1
公开(公告)日：2012-01-26
申请号：PCT/US2010/052785
申请日：2010-10-15
申请人： TESSERA , INC. , OGANESIAN, Vage , HABA, Belgacem , MITCHELL, Craig , MOHAMMED, Ilyas , SAVALIA, Piyush
发明人： OGANESIAN, Vage , HABA, Belgacem , MITCHELL, Craig , MOHAMMED, Ilyas , SAVALIA, Piyush
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , B24C1/045 , B24C3/322 , H01L23/481 , H01L23/4985 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2224/03464 , H01L2224/05009 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/06181 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01061 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2224/05552 , H01L2924/00
摘要： A method of fabricating a microelectronic unit 210 includes providing a semiconductor element 220 having a front 222 and rear surface 221 remote from the front surface, forming at least one opening 230 extending from the rear surface 221 through the semiconductor element 220 towards the front surface 222 by directing a jet of fine abrasive particles towards the semiconductor element, forming at least one second opening 240 extending from the first opening 230 to a bottom surface 251 of one conductive pad 250 exposed at the front surface 222, and forming at least one conductive contact 290 and at least one conductive interconnect 280a, 280b together. Each conductive interconnect 280a, 280b can extend within one or more of the first openings 230 and can be coupled to at least one conductive pad 250.
摘要翻译：制造微电子单元210的方法包括提供具有远离前表面的前222和后表面221的半导体元件220，形成从后表面221穿过半导体元件220朝向前表面222延伸的至少一个开口230 通过将精细磨料颗粒的射流引向半导体元件，形成从第一开口230延伸到暴露在前表面222处的一个导电焊盘250的底表面251的至少一个第二开口240，并形成至少一个导电接触 290和至少一个导电互连280a，280b在一起。每个导电互连280a，280b可以在一个或多个第一开口230内延伸并且可以耦合到至少一个导电焊盘250。

8. 发明申请

WO2012011930A1 NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS 审中-公开
标题翻译：非线性形成三维导电元件
公开(公告)号：WO2012011930A1
公开(公告)日：2012-01-26
申请号：PCT/US2010/052633
申请日：2010-10-14
申请人： TESSERA, INC. , OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , MITCHELL, Craig , SAVALIA, Piyush
发明人： OGANESIAN, Vage , HABA, Belgacem , MOHAMMED, Ilyas , MITCHELL, Craig , SAVALIA, Piyush
IPC分类号： H01L21/58 , H01L23/48
CPC分类号： H01L21/76879 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L23/4985 , H01L23/5226 , H01L24/06 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A method of forming a conductive element (24) on a substrate (10) and the resulting assembly (80) are provided. The method includes forming a groove (22) in a sacrificial layer (20) overlying a dielectric region (18) disposed on a substrate (10). The groove (22) preferably extends along a sloped surface (16) of the substrate (10). The sacrificial layer (20) is preferably removed by a non-photolithographic method, such as ablating with a laser (70), mechanical milling, or sandblasting. A conductive element (24) is formed in the groove (22). The grooves (22) and conductive elements (124) may be formed along any surface of the substrate (110), including within trenches (128) and vias (121) formed therein, and may connect to conductive pads (150) on the front (114) and/or rear surface (112) of the substrate (110). The conductive elements (24) are preferably formed by plating and may or may not conform to the surface of the substrate (10).
摘要翻译：提供了在基板（10）上形成导电元件（24）的方法和所得到的组件（80）。该方法包括在覆盖设置在基板（10）上的电介质区域（18）上的牺牲层（20）中形成凹槽（22）。槽（22）优选地沿衬底（10）的倾斜表面（16）延伸。牺牲层（20）优选通过非光刻方法去除，例如用激光（70）烧蚀，机械研磨或喷砂。导电元件（24）形成在凹槽（22）中。沟槽（22）和导电元件（124）可以沿着衬底（110）的任何表面形成，包括在其中形成的沟槽（128）和通孔（121）内，并且可以连接到前面的导电焊盘（150）（114）和/或背表面（112）。导电元件（24）优选地通过电镀形成，并且可以或不符合基板（10）的表面。

9. 发明申请

WO2012078213A1 HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS 审中-公开
标题翻译：高密度三维集成电容器
公开(公告)号：WO2012078213A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/044026
申请日：2011-07-14
申请人： TESSERA INC , MOHAMMED, Ilyas , HABA, Belgacem , UZOH, Cyprian , SAVALIA, Piyush , OGANESIAN, Vage
发明人： MOHAMMED, Ilyas , HABA, Belgacem , UZOH, Cyprian , SAVALIA, Piyush , OGANESIAN, Vage
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48
CPC分类号： H01L28/91 , H01L23/481 , H01L28/60 , H01L2223/6622 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A capacitor 340 includes a substrate 320 having a first surface 321, a second surface 322 remote from the first surface, and a through opening 330 extending between the first and second surfaces, first and second metal elements 360, 370, and a capacitor dielectric layer 380 separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element 360 is exposed at the first surface 321 and extends into the through opening 330. The second metal element 370 is exposed at the second surface 322 and extends into the through opening 330. The first and second metal elements 360, 370 are electrically connectable to first and second electric potentials. The capacitor dielectric layer 380 has an undulating shape.
摘要翻译：电容器340包括具有第一表面321，远离第一表面的第二表面322和在第一和第二表面之间延伸的通孔330的基底320，第一和第二金属元件360,370以及电容器电介质层 380至少在所述通孔内分离和绝缘所述第一和第二金属元件。第一金属元件360在第一表面321处露出并延伸到通孔330中。第二金属元件370在第二表面322处露出并延伸到通孔330中。第一和第二金属元件360,370是电连接到第一和第二电位。电容器介电层380具有波状形状。

10. 发明申请

WO2012061199A2 NO FLOW UNDERFILL 审中-公开
标题翻译：无流动性不足
公开(公告)号：WO2012061199A2
公开(公告)日：2012-05-10
申请号：PCT/US2011/058080
申请日：2011-10-27
申请人： TESSERA, INC. , HABA, Belgacem , MOHAMMED, Ilyas , CHAU, Ellis , LEE, Sang II , DESAI, Kishor
发明人： HABA, Belgacem , MOHAMMED, Ilyas , CHAU, Ellis , LEE, Sang II , DESAI, Kishor
IPC分类号： H01L21/56
CPC分类号： H01L23/49811 , H01L21/563 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/1601 , H01L2224/1605 , H01L2224/16225 , H01L2224/1703 , H01L2224/73104 , H01L2224/73204 , H01L2224/81143 , H01L2224/81193 , H01L2224/814 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/8349 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要： A method for making a microelectronic assembly includes providing a microelectronic element 30 with first conductive elements and a dielectric element 50 with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts 40 and other of the first or second conductive elements may include a bond metal 10 disposed between some of the conductive posts 40. An underfill layer 60 may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer 60 and at least deform the bond metal 10. The microelectronic element 30 and the dielectric element 50 can be heated to join them together. The height of the posts 40 above the surface may be at least forty percent of a distance between surfaces of the microelectronic element 30 and dielectric element 50.
摘要翻译：制造微电子组件的方法包括提供具有第一导电元件的微电子元件30和具有第二导电元件的电介质元件50。第一导电元件或第二导电元件中的至少一些可以是导电柱40，并且第一导电元件或第二导电元件中的另一个可以包括设置在一些导电柱40之间的键合金属10.底部填充层60可以过多地的第一或第二导电元件。第一导电元件中的至少一个可以朝向第二导电元件中的另一个移动，使得柱刺穿底部填充层60并且至少使键合金属10变形。微电子元件30和介电元件50可以被加热到加入他们在一起。在表面之上的柱40的高度可以是微电子元件30和电介质元件50的表面之间的距离的至少百分之四十。

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