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1. 发明授权

US07079424B1 Methods and systems for reducing erase times in flash memory devices 有权
标题翻译：用于减少闪存设备中擦除时间的方法和系统
公开(公告)号：US07079424B1
公开(公告)日：2006-07-18
申请号：US10945914
申请日：2004-09-22
申请人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
发明人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
IPC分类号： G11C11/34
CPC分类号： G11C16/107 , G11C16/16 , G11C16/3468
摘要： A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.
摘要翻译：提供一种用于擦除具有衬底，控制栅极，浮置栅极，源极区域和漏极区域的存储器单元的方法。该方法包括对存储器单元预编程以将存储器单元的阈值电压升高到第一预定电平，其中预编程存储器单元不包括用于确保存储器单元的阈值电压已被提高的验证过程到第一预定水平。可以擦除存储器单元以将存储器单元的阈值电压降低到第二预定电平。

2. 发明授权

US06747900B1 Memory circuit arrangement for programming a memory cell 有权
标题翻译：用于对存储器单元进行编程的存储器电路装置
公开(公告)号：US06747900B1
公开(公告)日：2004-06-08
申请号：US10348732
申请日：2003-01-21
申请人： Sheunghee Park , Ming Sang Kwan
发明人： Sheunghee Park , Ming Sang Kwan
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0416
摘要： A memory circuit for programming a target cell is disclosed. According to one embodiment, the memory circuit comprises the target cell having a drain terminal connected to a bit line. A drain voltage is coupled to the bit line and supplies a voltage greater than a ground voltage, while a gate voltage is coupled to a gate terminal of the target cell and supplies a voltage greater the ground voltage. A source voltage is coupled to a source terminal of the target cell and supplies a voltage less than the ground voltage, and a substrate voltage is coupled to a substrate of the target cell and supplies a voltage less than the ground voltage.
摘要翻译：公开了一种用于编程目标单元的存储电路。根据一个实施例，存储器电路包括具有连接到位线的漏极端子的目标单元。漏极电压耦合到位线，并提供大于接地电压的电压，而栅极电压耦合到目标单元的栅极端子并提供大于接地电压的电压。源极电压耦合到目标单元的源极端子并且提供小于接地电压的电压，并且将衬底电压耦合到目标单元的衬底并且提供小于接地电压的电压。

3. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

4. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

5. 发明授权

US07154141B2 Source side programming 有权
公开(公告)号：US07154141B2
公开(公告)日：2006-12-26
申请号：US09777007
申请日：2001-02-02
申请人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
发明人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/10
摘要： A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.

6. 发明授权

US5652155A Method for making semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant 失效
标题翻译：制造半导体电路的方法包括由于杂质注入而导致的劣化降低的非ESD晶体管
公开(公告)号：US5652155A
公开(公告)日：1997-07-29
申请号：US550424
申请日：1995-10-30
申请人： David K. Y. Liu , Ming Sang Kwan , Chi Chang
发明人： David K. Y. Liu , Ming Sang Kwan , Chi Chang
IPC分类号： H01L27/02 , H01L21/266
CPC分类号： H01L27/0266 , Y10S438/982
摘要： A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transistors includes forming the ESD transistors of the circuit at a predetermined angular offset from the non-ESD transistor, and performing the second dopant implant at a predetermined tilt implant angle, wherein the non-ESD transistor has reduced encroachment of the impurity implant. A plurality of transistors formed on a semiconductor wafer include a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.
摘要翻译：一种用于减少杂质注入侵入半导体电路中的非ESD晶体管中的沟道区域的方法，所述非ESD晶体管接收第一和第二注入掺杂剂，并且包括多个ESD晶体管的电路包括形成ESD 晶体管，其以非ESD晶体管的预定角度偏移，并以预定的倾斜注入角执行第二掺杂剂注入，其中非ESD晶体管具有减少的杂质注入侵入。形成在半导体晶片上的多个晶体管包括多个非ESD晶体管，所述多个非ESD晶体管包括间隔区域和侵入间隔区域的杂质注入区域，以及多个ESD晶体管，所述多个ESD晶体管形成在非ESD晶体管的预定角度偏移处。此外，多个ESD晶体管包括比非ESD晶体管的杂质注入区域更远的间隔区域和杂质注入区域。

7. 发明申请

US20080279014A1 MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY 有权
标题翻译：闪存存储器的多相WORDLINE擦除
公开(公告)号：US20080279014A1
公开(公告)日：2008-11-13
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

8. 发明申请

US20100322006A1 NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME 审中-公开
标题翻译：具有堆叠的选择门结构的NAND存储器单元和用于形成其的处理
公开(公告)号：US20100322006A1
公开(公告)日：2010-12-23
申请号：US12489226
申请日：2009-06-22
申请人： Ming Sang Kwan , Shenqing Fang , Youseok Suh , Michael Van Buskirk
发明人： Ming Sang Kwan , Shenqing Fang , Youseok Suh , Michael Van Buskirk
IPC分类号： G11C16/04 , H01S4/00
CPC分类号： G11C16/16 , G11C16/0483 , Y10T29/49002
摘要： A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate and a second select gate, that includes a second plurality of elements, is coupled to the plurality of wordlines. The distances between one element of the first and the second plurality of elements and the plurality of wordlines are the same as the distances that exist between each wordline of the plurality of wordlines.
摘要翻译：公开了一种存储单元串。存储单元串包括包括第一多个元件的第一选择栅极。多个字线耦合到第一选择栅极，并且包括第二多个元件的第二选择栅极耦合到多个字线。第一和第二多个元件的一个元件与多个字线之间的距离与存在于多个字线的每个字线之间的距离相同。

9. 发明授权

US5981994A Method and semiconductor circuit for maintaining integrity of field threshold voltage requirements 失效
标题翻译：用于保持场阈值电压要求完整性的方法和半导体电路
公开(公告)号：US5981994A
公开(公告)日：1999-11-09
申请号：US550142
申请日：1995-10-30
申请人： David K. Y. Liu , Jian Chen , Ming Sang Kwan
发明人： David K. Y. Liu , Jian Chen , Ming Sang Kwan
IPC分类号： H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , H01L29/792 , H01L29/94
CPC分类号： H01L29/42324 , H01L27/115
摘要： A method for maintaining a high field threshold voltage in a plurality of transistors of reduced size in a periphery region of a Flash EPROM semiconductor circuit includes forming a first polysilicon layer as a floating poly in a predetermined number of transistors of the plurality of transistors in the periphery region, and forming a second polysilicon layer as a common gate line in the plurality of transistors, wherein the predetermined number of transistors prevent breakdown of the plurality of transistors below a predetermined field threshold voltage. In one aspect, the field oxide layer has a thickness of about 2500 angstroms. A plurality of transistors formed in a substrate of a periphery region of a Flash EPROM semiconductor circuit includes a first predetermined number of periphery transistors having a floating poly and a common gate line, and a second predetermined number of periphery transistors having the common gate line and adjacent the first predetermined number of transistors, the first predetermined number of transistors preventing breakdown of the second predetermined number of periphery transistors below a predetermined field threshold voltage.
摘要翻译：一种用于在闪存EPROM半导体电路的外围区域中维持减小尺寸的多个晶体管中的高场阈值电压的方法包括在多个晶体管的预定数量的晶体管中形成作为浮动多晶硅的第一多晶硅层，并且在所述多个晶体管中形成第二多晶硅层作为公共栅极线，其中所述预定数量的晶体管防止所述多个晶体管的击穿低于预定场阈值电压。在一个方面，场氧化物层具有约2500埃的厚度。形成在闪存EPROM半导体电路的周边区域的基板中的多个晶体管包括具有浮置多晶硅和公共栅极线的第一预定数量的周边晶体管，以及具有共同栅极线的第二预定数量的外围晶体管，与第一预定数量的晶体管相邻，第一预定数量的晶体管防止第二预定数量的外围晶体管击穿超过预定场阈值电压。

10. 发明授权

US5882985A Reduction of field oxide step height during semiconductor fabrication 失效
标题翻译：在半导体制造期间减小场氧化物步长
公开(公告)号：US5882985A
公开(公告)日：1999-03-16
申请号：US541927
申请日：1995-10-10
申请人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
发明人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： A method for reducing the steep step at the edge of a locally oxidized, field oxide boundary region as a result of using the local oxidation of silicon (LOCOS) method to isolate the active regions of a semiconductor wafer. The reduction is carried out by applying a planarizing layer to the field oxide layer and then etching back the planarizing layer and field oxide layer to a desired thickness.
摘要翻译：作为使用硅的局部氧化（LOCOS）方法的局部氧化的场氧化物边界区域的边缘处的陡峭步骤的方法来隔离半导体晶片的有源区域的方法。通过将平坦化层施加到场氧化物层，然后将平坦化层和场氧化物层回蚀刻到期望的厚度来进行还原。

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