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1. 发明申请

US20100322006A1 NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME 审中-公开
标题翻译：具有堆叠的选择门结构的NAND存储器单元和用于形成其的处理
公开(公告)号：US20100322006A1
公开(公告)日：2010-12-23
申请号：US12489226
申请日：2009-06-22
申请人： Ming Sang Kwan , Shenqing Fang , Youseok Suh , Michael Van Buskirk
发明人： Ming Sang Kwan , Shenqing Fang , Youseok Suh , Michael Van Buskirk
IPC分类号： G11C16/04 , H01S4/00
CPC分类号： G11C16/16 , G11C16/0483 , Y10T29/49002
摘要： A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate and a second select gate, that includes a second plurality of elements, is coupled to the plurality of wordlines. The distances between one element of the first and the second plurality of elements and the plurality of wordlines are the same as the distances that exist between each wordline of the plurality of wordlines.
摘要翻译：公开了一种存储单元串。存储单元串包括包括第一多个元件的第一选择栅极。多个字线耦合到第一选择栅极，并且包括第二多个元件的第二选择栅极耦合到多个字线。第一和第二多个元件的一个元件与多个字线之间的距离与存在于多个字线的每个字线之间的距离相同。

2. 发明申请

US20080285354A1 Self reference sensing system and method 审中-公开
标题翻译：自我参考感测系统及方法
公开(公告)号：US20080285354A1
公开(公告)日：2008-11-20
申请号：US11804170
申请日：2007-05-16
申请人： Soo-Yong Park , Takao Akaogi , Michael Van Buskirk
发明人： Soo-Yong Park , Takao Akaogi , Michael Van Buskirk
IPC分类号： G11C11/34 , G11C5/14
CPC分类号： G11C16/28 , G11C16/0458
摘要： A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication.
摘要翻译：描述了自感基准系统和方法。自我检测参考系统和方法有助于有效准确地访问信息。在一个实施例中，自感基准系统包括主共源共栅分量，自参考分量和比较验证分量。主级联组件接收第一电流值和第二电流值的输入。自参考分量建立多个数据指示，其中基于第一当前值与第二当前值的比较来建立第一数据指示。比较验证部件验证第二数据指示。

3. 发明申请

US20060067105A1 Control of memory devices possessing variable resistance characteristics 有权
标题翻译：具有可变电阻特性的存储器件的控制
公开(公告)号：US20060067105A1
公开(公告)日：2006-03-30
申请号：US10983919
申请日：2004-11-08
申请人： Tzu-Ning Fang , Michael Van Buskirk , Colin Bill
发明人： Tzu-Ning Fang , Michael Van Buskirk , Colin Bill
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.
摘要翻译：采用至少一个恒定电流源的系统和方法促进有机存储器单元的编程和/或采用至少一个恒定电压源以便于擦除存储器件。本发明用于单个存储器单元装置和存储单元阵列。使用恒流源防止编程期间的电流尖峰，并允许在写周期期间精确控制存储单元的状态，而与电池的电阻无关。使用恒定电压源在擦除周期期间为存储器单元提供稳定的负载，并且允许跨过存储器单元的精确的电压控制，尽管在该过程中电池电阻的大的动态变化。

4. 发明授权

US06583479B1 Sidewall NROM and method of manufacture thereof for non-volatile memory cells 有权
标题翻译：侧壁NROM及其制造方法用于非易失性存储单元
公开(公告)号：US06583479B1
公开(公告)日：2003-06-24
申请号：US09688936
申请日：2000-10-16
申请人： Richard M. Fastow , Shane C. Hollmer , Pau-Ling Chen , Michael Van Buskirk , Masaaki Higashitani
发明人： Richard M. Fastow , Shane C. Hollmer , Pau-Ling Chen , Michael Van Buskirk , Masaaki Higashitani
IPC分类号： H01L31062
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C16/0491 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array of NROM transistors can be formed without adversely affecting the channel length and therefore the operational performance of the transistor.
摘要翻译：公开了一种用于存储器阵列的非易失性只读存储晶体管。非易失性只读存储器晶体管具有在衬底中形成的沟槽中制造的基本上垂直取向的通道。通道长度取决于沟槽的深度，因此可以形成NROM晶体管的密集阵列，而不会不利地影响沟道长度，从而不影响晶体管的操作性能。

5. 发明授权

US06501681B1 Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories 有权
标题翻译：在擦除验证期间使用低漏极偏置，以确保在声纳非易失性存储器中完全去除氮化物中的残留电荷
公开(公告)号：US06501681B1
公开(公告)日：2002-12-31
申请号：US09684694
申请日：2000-10-04
申请人： Michael Van Buskirk , Narbeh Derhacobian
发明人： Michael Van Buskirk , Narbeh Derhacobian
IPC分类号： G11C1606
CPC分类号： G11C16/344
摘要： An erase-verify operation is performed on a nonvolatile memory cell with an oxide-nitride-oxide structure by using a low drain bias voltage to allow residual charge remaining in the nitride layer after a typical erase operation to be detected effectively with a high degree of sensitivity.
摘要翻译：通过使用低漏极偏置电压，在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上进行擦除验证操作，以允许在典型的擦除操作之后残留在氮化物层中的剩余电荷以高度灵敏度。

6. 发明申请

US20060049435A1 Vertical JFET as used for selective component in a memory array 审中-公开
标题翻译：用于存储器阵列中的选择性组件的垂直JFET
公开(公告)号：US20060049435A1
公开(公告)日：2006-03-09
申请号：US10935301
申请日：2004-09-07
申请人： Colin Bill , Michael Van Buskirk
发明人： Colin Bill , Michael Van Buskirk
IPC分类号： H01L29/80
CPC分类号： H01L27/10 , H01L27/098
摘要： Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell in a memory array while increasing device density in the memory cell array. A vertical JFET is described to which voltages can be selectively applied to control internal current flow there through, which in turn can be employed to manipulate the state of a polymer memory cell coupled to the vertical JFET. By mitigating gaps between gates, or wordlines, and drains of the vertical JFETs, feature size can be reduced to permit increased device density. Furthermore, vertical JFETs in the array can be coupled to gates on only two opposite sides, permitting the JFETs to be arranged without gate crossbars between them, further increasing device density. In this manner, the present invention provides switching characteristics to a memory cell and overcomes problematic bulkiness associated with conventional MOS devices.
摘要翻译：公开了系统和方法，其有助于提供存储器阵列中的聚合物存储器单元的选择性功能，同时增加存储器单元阵列中的器件密度。描述了可以选择性地施加电压以控制其中的内部电流的垂直JFET，其又可以用于操纵耦合到垂直JFET的聚合物存储器单元的状态。通过减轻栅极，字线和垂直JFET的漏极之间的间隙，可以减小特征尺寸以允许增加的器件密度。此外，阵列中的垂直JFET可以仅在两个相对的侧面上耦合到栅极，从而允许JFET布置成没有栅极交叉条之间，进一步增加器件密度。以这种方式，本发明向存储单元提供开关特性并且克服了与常规MOS器件相关的有问题的体积。

7. 发明授权

US6033955A Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture 有权
标题翻译：制造灵活划分的金属线段的方法，用于具有灵活的银行分区架构的同时操作的闪存设备
公开(公告)号：US6033955A
公开(公告)日：2000-03-07
申请号：US159023
申请日：1998-09-23
申请人： Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
发明人： Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
IPC分类号： G11C16/04 , G11C5/00 , G11C8/10 , G11C8/12 , G11C16/08 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/063 , G11C16/08 , G11C8/10 , G11C8/12
摘要： A method of forming flexibly partitioned metal line segments 10 and 12 for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer 2 comprising a plurality of basic metal layer segments 2a, 2b, 2c, . . . 2j separated by a plurality of gaps 6a, 6b, 6c, . . . 6i, each of the gaps having a predefined gap interval length, and providing a metal option layer 8 comprising a plurality of metal option layer segments on the basic metal layer 2, the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.
摘要翻译：在具有柔性库分隔结构的同时操作的闪速存储器件中形成用于单独存储体的柔性分隔的金属线段10和12的方法包括以下步骤：提供包括多个基本金属层段2a，2b的基本金属层2 ，2c，。。。 2j由多个间隙6a，6b，6c，...分开。。。如图6i所示，每个间隙具有预定的间隙间隔长度，并且提供包括在基本金属层2上的多个金属可选层段的金属选择层8，金属选择层段与基本金属层段之间的间隙重叠，但是留下一个间隙打开，以形成用于单独存储体的金属线段。

8. 发明授权

US06005803A Memory address decoding circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 有权
标题翻译：存储器地址解码电路，用于同时运行闪存器件，具有灵活的存储体分区结构
公开(公告)号：US06005803A
公开(公告)日：1999-12-21
申请号：US159342
申请日：1998-09-23
申请人： Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
发明人： Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
IPC分类号： G11C16/06 , G11C8/12 , G11C16/02 , G11C16/08 , G11C7/00
CPC分类号： G11C8/12 , G11C16/08
摘要： A decoding circuit 54 for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder 44, a lower bank decoder 58, an upper bank decoder 56, and a plurality of flexibly partitioned conductive lines coupled between the upper and lower bank decoders 56 and 58. The flexibly partitioned conductive lines 60, 62, 64, . . . 74 provide a plurality of bank address pre-decoding bits for the X-decoder 44 to row decode the memory cells along the respective word lines in the memory array 20. The memory array 20 includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are coupled to two Y-decoders 32 and 34 which provide column decoding for the memory cells in the upper and lower memory banks.
摘要翻译：用于具有灵活存储体分区体系结构的同时操作的非易失性存储器件的解码电路54包括X解码器44，下部存储体解码器58，上部存储体解码器56和多个柔性分隔的导线，和下部分组解码器56和58.柔性分隔的导线60,62,64。。。 74提供多个用于X解码器44的存储体地址预解码位，以沿着存储器阵列20中的相应字线对存储器单元进行解码。存储器阵列20包括多个灵活分割的位线，包括第一和第二位线段将存储器阵列分隔成上部和下部存储体。上存储体和下存储体中的位线段耦合到两个Y解码器32和34，它们为上和下存储体中的存储单元提供列解码。

9. 发明申请

US20060113524A1 Polymer-based transistor devices, methods, and systems 审中-公开
标题翻译：基于聚合物的晶体管器件，方法和系统
公开(公告)号：US20060113524A1
公开(公告)日：2006-06-01
申请号：US11000685
申请日：2004-12-01
申请人： Colin Bill , Michael Van Buskirk , Zhida Lan , John Ennals , Tzu-Ning Fang
发明人： Colin Bill , Michael Van Buskirk , Zhida Lan , John Ennals , Tzu-Ning Fang
IPC分类号： H01L29/08
CPC分类号： H01L51/102 , H01L51/0525
摘要： One aspect of the present invention relates to a semiconductor transistor device with an annular gate surrounding, at least in part, a channel that conducts current between a first and second source/drain. Another aspect of the present invention relates to a semiconductor transistor device having an annular gate and containing a channel composed of a polymer material. Yet another aspect of the present invention relates to fabrication of a device utilizing a polymer channel surrounded, at least in part, by an annular gate. Still yet another aspect of the present invention relates to a system with a means to control (and/or amplify) current via an annular gate surrounding a channel which conducts current between a first and second source/drain. Still other aspects of the present invention include devices incorporating the present invention's devices, systems and methods such as computers, memory, handhelds and electronic devices.
摘要翻译：本发明的一个方面涉及一种具有环形栅极的半导体晶体管器件，该环形栅极至少部分地包围在第一和第二源极/漏极之间传导电流的沟道。本发明的另一方面涉及一种具有环形栅极并且包含由聚合物材料构成的通道的半导体晶体管器件。本发明的另一方面涉及使用至少部分由环形栅极包围的聚合物通道的装置的制造。本发明的另一方面涉及一种具有通过围绕在第一和第二源极/漏极之间传导电流的沟道的环形栅极来控制（和/或放大）电流的装置的系统。本发明的其它方面包括结合本发明的装置，诸如计算机，存储器，手持设备和电子装置的系统和方法的装置。

10. 发明授权

US07038948B2 Read approach for multi-level virtual ground memory 有权
标题翻译：多级虚拟接地存储器的读取方法
公开(公告)号：US07038948B2
公开(公告)日：2006-05-02
申请号：US10946809
申请日：2004-09-22
申请人： Darlene Hamilton , Fatima Bathul , Masato Horiike , Eugen Gershon , Michael Van Buskirk
发明人： Darlene Hamilton , Fatima Bathul , Masato Horiike , Eugen Gershon , Michael Van Buskirk
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/34 , G11C16/3418 , G11C2211/5634
摘要： The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.
摘要翻译：本发明涉及用于确定双面ONO闪速存储器单元中的位的电平的技术，其中双面ONO闪存单元的每个位可以被编程为多个电平。本发明的一个或多个方面考虑到一位上的电荷电平对另一位可能具有的影响，或称为互补位干扰的影响。被称为跨导的度量被用于使位电平确定提供更大程度的分辨率和精度。以这种方式，根据本发明的一个或多个方面确定比特级别减轻了错误或错误的读取。

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