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1. 发明授权

US06291848B1 Integrated circuit capacitor including anchored plugs 有权
标题翻译：集成电路电容器，包括固定插头
公开(公告)号：US06291848B1
公开(公告)日：2001-09-18
申请号：US09364767
申请日：1999-07-30
申请人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L21/76838 , H01L27/10817 , H01L27/10852 , H01L28/60
摘要： An integrated circuit capacitor includes a substrate, a first dielectric layer adjacent the substrate and having a first trench therein, and a first metal plug extending upwardly into the first trench. An interconnection line overlies the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. A second dielectric layer is on the interconnection line and has a second trench therein. A second metal plug extends upwardly into the second trench. More particularly, the second metal plug includes a body portion extending upwardly into the second trench, and anchor portions connected to the body portion and engaging the anchoring recesses to anchor the second metal plug to the interconnection line. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line.
摘要翻译：集成电路电容器包括衬底，与衬底相邻并且在其中具有第一沟槽的第一电介质层和向上延伸到第一沟槽中的第一金属插塞。互连线覆盖在第一沟槽上并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。第二介电层位于互连线上并且在其中具有第二沟槽。第二金属插头向上延伸到第二沟槽中。更具体地，第二金属插头包括向上延伸到第二沟槽中的主体部分，以及连接到主体部分并且与固定凹部接合并将第二金属插头固定到互连线的锚定部分。由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。

2. 发明授权

US6103586A Method for making integrated circuit capacitor including anchored plugs 有权
标题翻译：制造集成电路电容器包括固定插头的方法
公开(公告)号：US6103586A
公开(公告)日：2000-08-15
申请号：US364025
申请日：1999-07-30
申请人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/768 , H01L27/108 , H01L21/20
CPC分类号： H01L28/60 , H01L21/76838 , H01L21/76895
摘要： A method for making an integrated circuit capacitor includes forming a first dielectric layer adjacent a substrate, forming a first opening in the first dielectric layer, filling the first opening with a conductive material to define a first metal plug, and forming a trench in the first dielectric layer adjacent the first metal plug. An interconnection line lines the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. The method further includes forming a second dielectric layer on the interconnection line, forming a second opening in the second dielectric layer, and filling the second opening with a conductive metal to define a second metal plug having a body portion and anchor portions extending downward from the body portion for engaging the anchoring recesses to anchor the second metal plug. A second trench is formed in the second dielectric layer adjacent the second metal plug, and is aligned with the first trench. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line. The electrodes and dielectric layers of the capacitor are formed so that they line the second trench.
摘要翻译：一种制造集成电路电容器的方法包括：在基片附近形成第一电介质层，在第一电介质层中形成第一开口，用导电材料填充第一开口以限定第一金属插塞，并在第一电介质层中形成沟槽电介质层邻近第一金属插头。互连线对准第一沟槽并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。所述方法还包括在所述互连线上形成第二电介质层，在所述第二电介质层中形成第二开口，并用导电金属填充所述第二开口，以限定第二金属插塞，所述第二金属插塞具有主体部分和从所述第二介质层向下延伸的固定部分主体部分，用于接合所述锚定凹部以锚定所述第二金属插塞。在与第二金属插塞相邻的第二电介质层中形成第二沟槽，并且与第一沟槽对准。由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。电容器的电极和电介质层形成为使得它们与第二沟槽对齐。

3. 发明授权

US06492712B1 High quality oxide for use in integrated circuits 有权
标题翻译：高品质氧化物用于集成电路
公开(公告)号：US06492712B1
公开(公告)日：2002-12-10
申请号：US09597077
申请日：2000-06-20
申请人： Yuanning Chen , Sundar Srinivasan Chetlur , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Yuanning Chen , Sundar Srinivasan Chetlur , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L21316
CPC分类号： C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/28185 , H01L21/28211 , H01L21/28273 , H01L21/31662 , H01L29/513 , H01L29/518
摘要： An oxide for use in integrated circuits is substantially stress-free both in the bulk and at the interface between the substrate and the oxide. The interface is planar and has a low interface trap density (Nit). The oxide has a low defect density and may have a thickness of less than 1.5 nm or less.
摘要翻译：用于集成电路的氧化物在本体和衬底与氧化物之间的界面处基本上是无应力的。界面是平面的，并且具有低的界面陷阱密度（Nit）。氧化物的缺陷密度低，可以具有小于1.5nm以下的厚度。

4. 发明授权

US06375541B1 Polishing fluid polishing method semiconductor device and semiconductor device fabrication method 有权
标题翻译：抛光液抛光法半导体器件及半导体器件制造方法
公开(公告)号：US06375541B1
公开(公告)日：2002-04-23
申请号：US09483576
申请日：2000-01-14
申请人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： B24B100
CPC分类号： B24B37/005 , B24B37/044 , C09G1/02
摘要： A polishing fluid comprising a distributed organic phase and a continuous aqueous phase. The distributed phase has at least one complexing agent and the aqueous phase has abrasive particles dispersed therein. Reaction products generated during polishing interact with the complexing agent(s) to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.
摘要翻译：包括分布有机相和连续水相的抛光液。分布相具有至少一种络合剂，水相中分散有磨料颗粒。在抛光过程中产生的反应产物与络合剂相互作用形成有机金属络合物。进一步公开了一种利用抛光液的抛光方法，半导体器件和半导体器件制造方法。

5. 发明授权

US06458016B2 Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method 有权
标题翻译：抛光液，抛光法，半导体器件及半导体器件的制造方法
公开(公告)号：US06458016B2
公开(公告)日：2002-10-01
申请号：US09894116
申请日：2001-06-28
申请人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sailesh Mansinh Merchant , Sudhanshu Misra , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： B24B2118
CPC分类号： B24B37/005 , B24B37/044 , C09G1/02
摘要： A polishing fluid comprising a distributed organic phase and a continuous aqueous phase. The distributed phase has at least one complexing agent and the aqueous phase has abrasive particles dispersed therein. Reaction products generated during polishing interact with the complexing agent(s) to form organometallic complexes. Further disclosed is a polishing method, a semiconductor device and semiconductor device fabrication method utilizing the polishing fluid.
摘要翻译：包括分布有机相和连续水相的抛光液。分布相具有至少一种络合剂，水相中分散有磨料颗粒。在抛光过程中产生的反应产物与络合剂相互作用形成有机金属络合物。进一步公开了一种利用抛光液的抛光方法，半导体器件和半导体器件制造方法。

6. 发明授权

US06204186B1 Method of making integrated circuit capacitor including tapered plug 有权
标题翻译：制造集成电路电容器包括锥形插头的方法
公开(公告)号：US06204186B1
公开(公告)日：2001-03-20
申请号：US09364366
申请日：1999-07-30
申请人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
发明人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L21311
CPC分类号： H01L28/60 , H01L21/76804 , H01L27/10808 , H01L27/10852 , H01L28/40
摘要： A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.
摘要翻译：一种制造电容器的方法包括以下步骤：在衬底上形成互连线，在互连线上沉积第一介电层，以及蚀刻第一介电层中的通孔。通孔具有朝向基板的方向增加的锥形宽度。此外，该方法包括用导电金属填充通孔以形成金属插塞，并且在金属插塞的上部周围蚀刻第一电介质层中的沟槽。金属插头具有将其固定到电介质层中的锥形宽度。第二电介质层沉积在金属插塞附近，并且上电极沉积在第二电介质层上。优选地，沉积下电极以对准沟槽并接触金属插塞。

7. 发明授权

US06249016B1 Integrated circuit capacitor including tapered plug 有权
标题翻译：集成电路电容器包括锥形插头
公开(公告)号：US06249016B1
公开(公告)日：2001-06-19
申请号：US09364603
申请日：1999-07-30
申请人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
发明人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/40
摘要： An integrated circuit capacitor includes a first dielectric layer adjacent a substrate and having a trench therein, and a metal plug comprising an upper portion extending upwardly into the trench, and a lower portion disposed in the first dielectric layer. The lower portion has a tapered width which increases in a direction toward the substrate to thereby secure the metal plug in the dielectric layer. Preferably, the upper portion is also tapered. Furthermore, a second dielectric layer is adjacent the metal plug with an upper electrode thereon.
摘要翻译：集成电路电容器包括与衬底相邻并且在其中具有沟槽的第一电介质层和包括向上延伸到沟槽中的上部的金属插塞和设置在第一电介质层中的下部。下部具有朝向基板的方向增加的锥形宽度，从而将金属塞固定在电介质层中。优选地，上部也是锥形的。此外，第二电介质层与其上的上电极邻近金属插塞。

8. 发明授权

US06358790B1 Method of making a capacitor 有权
标题翻译：制作电容器的方法
公开(公告)号：US06358790B1
公开(公告)日：2002-03-19
申请号：US09250501
申请日：1999-02-16
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L218234
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a plug, planarizing the substrate, patterning the substrate to expose the first material, forming an electrode material layer over the substrate, and patterning the electrode material layer, whereby the first material is substantially encapsulated by the electrode material layer.
摘要翻译：本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽以形成插头，使衬底平坦化，图案化衬底以露出第一材料，在衬底上形成电极材料层，以及图案化电极材料层，由此第一材料基本上被电极材料层封装。

9. 发明授权

US06331484B1 Titanium-tantalum barrier layer film and method for forming the same 有权
标题翻译：钛 - 钽阻挡层膜及其形成方法
公开(公告)号：US06331484B1
公开(公告)日：2001-12-18
申请号：US09519193
申请日：2000-03-06
申请人： Siddhartha Bhowmik , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy , Sidhartha Sen
发明人： Siddhartha Bhowmik , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy , Sidhartha Sen
IPC分类号： H01L214763
CPC分类号： H01L21/76864 , H01L21/76807 , H01L21/76841 , H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A titanium-tantalum barrier layer film for use in conjunction with an interconnect film such as copper and a method for forming the same provides a relatively titanium rich/tantalum deficient portion adjacent the interface it forms with a dielectric film and a relatively tantalum rich/titanium deficient portion adjacent the interface it forms with a conductive interconnect film formed over the barrier layer film. The titanium rich/tantalum deficient portion provides good adhesion to the dielectric film and the tantalum rich/titanium deficient portion forms a hetero-epitaxial interface with the interconnect film and suppresses the formation of inter-metallic compounds. A single titanium-tantalum film having a composition gradient from top-to-bottom may be formed using various techniques including PVD, CVD, sputter deposition using a sputtering target of homogeneous composition, and sputter deposition using multiple sputtering targets. A composite titanium-tantalum film consists of two separately formed films.
摘要翻译：用于与诸如铜的互连膜一起使用的钛 - 钽阻挡层膜及其形成方法提供了与其形成的界面相邻的富钛/钽缺陷部分，其与介电膜和相对富钽/钛与其形成的界面相邻的缺陷部分与在阻挡层膜上形成的导电互连膜形成。富钛/钽缺陷部分对电介质膜提供良好的粘附性，并且富钽/钛缺陷部分与互连膜形成异质外延界面并抑制金属间化合物的形成。可以使用包括PVD，CVD，使用均匀组合物的溅射靶的溅射沉积以及使用多个溅射靶的溅射沉积的各种技术来形成具有从顶部到底部的组成梯度的单个钛 - 钽膜。复合钛 - 钽薄膜由两个单独形成的薄膜组成。

10. 发明授权

US06319837B1 Technique for reducing dishing in Cu-based interconnects 有权
标题翻译：减少铜基互连中凹陷的技术
公开(公告)号：US06319837B1
公开(公告)日：2001-11-20
申请号：US09606833
申请日：2000-06-29
申请人： Sailesh Chittipeddi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Sailesh Chittipeddi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2100
CPC分类号： H01L21/7684
摘要： The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.
摘要翻译：本发明包括一种用于减少集成电路互连的凹陷的方法，包括以下步骤：在衬底上的镶嵌特征之上提供过量的互连材料，并平坦化衬底和互连材料以获得衬底中的互连。

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