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1. 发明授权

US6107875A Variable frequency class D modulator with built in soft clipping and frequency limiting 有权
标题翻译：具有内置软限幅和频率限制的变频D类调制器
公开(公告)号：US6107875A
公开(公告)日：2000-08-22
申请号：US173111
申请日：1998-10-15
申请人： Stuart W. Pullen , Patrick A. Begley , Donald R. Preslar
发明人： Stuart W. Pullen , Patrick A. Begley , Donald R. Preslar
IPC分类号： H03F3/217 , H03F3/38
CPC分类号： H03F3/2171 , H03F2200/351 , H03F2200/66
摘要： A class D amplifier 100 has an integrator 10, a comparator 12, and a frequency compensation and gain control (FCGC) circuit 40. The FCGC circuit 40 senses the output and reduces the gain in order to keep the sampling frequency high enough to avoid audio artifacts.
摘要翻译： D类放大器100具有积分器10，比较器12和频率补偿和增益控制（FCGC）电路40.FCGC电路40感测输出并减小增益，以便使采样频率保持足够高以避免音频文物。

2. 发明授权

US06768376B2 Dual mode class D amplifiers 失效
标题翻译：双模D类放大器
公开(公告)号：US06768376B2
公开(公告)日：2004-07-27
申请号：US10430756
申请日：2003-05-06
申请人： David Hoyt , Stuart W. Pullen , Patrick A. Begley , Arecio A. Hernandez , Jeffrey M. Strang
发明人： David Hoyt , Stuart W. Pullen , Patrick A. Begley , Arecio A. Hernandez , Jeffrey M. Strang
IPC分类号： H03F338
CPC分类号： H04B15/04 , H03F1/0261 , H03F3/2171
摘要： Pulse width modulated (“Class D”) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics that interfere with AM radio reception. This interference has precluded wide spread acceptance of class D amplifiers in products that include an AM radio. The amplifier described here uses a a harmonic avoidance modulator when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or the intermediate (IF) frequency thereof.
摘要翻译：脉冲宽度调制（“D类”）放大器和50 khz至2 MHz范围内的控制器可以产生干扰AM无线电接收的谐波。这种干扰阻碍了D类放大器在包括AM无线电的产品中的广泛接受。这里描述的放大器在使用AM无线电操作时使用谐波避免调制器，以避免在接收机选择的频率或其中间（IF）频率处产生谐波。

3. 发明授权

US06587670B1 Dual mode class D amplifiers 失效
标题翻译：双模D类放大器
公开(公告)号：US06587670B1
公开(公告)日：2003-07-01
申请号：US09342376
申请日：1999-06-29
申请人： David Hoyt , Stuart W. Pullen , Patrick A. Begley , Arecio A. Hernandez , Jeffrey M. Strang
发明人： David Hoyt , Stuart W. Pullen , Patrick A. Begley , Arecio A. Hernandez , Jeffrey M. Strang
IPC分类号： H04B110
CPC分类号： H04B15/04 , H03F1/0261 , H03F3/2171
摘要： Pulse width modulated (“Class D”) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics which interfere with AM radio reception. This has precluded wide spread acceptance of class D amplifiers in products with an AM radio. The amplifiers described here use a modified modulation technique when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or its intermediate (IF) frequency. One embodiment uses a harmonic avoidance modulator. A second embodiment uses two or more oscillators and tests for the least distorted output signal. A third embodiment switches the mode of operation to a class AB amplifier when an AM signal is amplified.
摘要翻译：脉冲宽度调制（“D类”）放大器和50 khz至2 MHz范围内的控制器可以产生干扰AM无线电接收的谐波。这已经阻止了具有AM收音机的产品中D类放大器的广泛接受。这里描述的放大器在使用AM无线电操作时使用修改的调制技术，以避免在接收机选择的频率或其中间（IF）频率处产生谐波。一个实施例使用谐波回避调制器。第二实施例使用两个或更多个振荡器和测试用于最小失真的输出信号。当AM信号被放大时，第三实施例将操作模式切换到AB类放大器。

4. 发明授权

US06492705B1 Integrated circuit air bridge structures and methods of fabricating same 失效
标题翻译：集成电路空气桥结构及其制造方法
公开(公告)号：US06492705B1
公开(公告)日：2002-12-10
申请号：US08658010
申请日：1996-06-04
申请人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
发明人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5221 , H01L2924/0002 , H01L2924/00
摘要： Airbridge structures and processes for making air bridge structures and integrated circuits are disclosed. One airbridge structure has metal conductors 24 encased in a sheath of dielectric material 249. The conductors extend across a cavity 244 and a semiconductor substrate 238. In one embodiment, the conductors traversing the cavity 244 are supported by posts 248 that extend from the substrate. In another embodiment, oxide posts 258 extend from the substrate to support the conductors. In another embodiment, trenches 101 are made in a device substrate 110 bonded to a handle substrate 100. The trenches are filled with a dielectric and a conductor pattern is formed over the filled trenches. The substrate material between the conductors is then removed to leave a pattern of posts 116, 114, 112 that included dielectrically encased conductors 106. In another bonded wafer embodiment, conductors 204 are encased in a dielectric above a sacrificial device region. The device region is isolated by suitably filled trenches. Vias 224, 226 in the dielectric 205 allow removal of the substrate material to form a cavity 208 beneath the conductors 204. Other embodiments included a conductor 42 encased in dielectric that is formed above a region from which sacrificial polysilicon is removed to form a cavity 66. It is still another embodiment the conductor 42 is enclosed in a dielectric above a cavity 66a from which device material is removed.
摘要翻译：公开了用于制造空气桥结构和集成电路的空中桥梁结构和工艺。一个空中桥结构具有包裹在电介质材料249的护套中的金属导体24.导体延伸穿过空腔244和半导体衬底238.在一个实施例中，穿过空腔244的导体由从衬底延伸的柱248支撑。在另一个实施例中，氧化物柱258从衬底延伸以支撑导体。在另一个实施例中，沟槽101被制成接合到手柄衬底100的器件衬底110.沟槽填充有电介质，并且导体图案形成在填充的沟槽。然后去除导体之间的衬底材料以留下包括介电封装的导体106的柱116,114,112的图案。在另一个接合晶片实施例中，导体204被封装在牺牲器件区域之上的电介质中。器件区域由适当填充的沟槽隔离。电介质205中的通孔224,226允许去除衬底材料以在导体204下方形成空腔208.其它实施例包括封装在电介质中的导体42，导电体42形成在除去牺牲多晶硅以形成空腔66的区域之上还有另一个实施例，导体42封闭在空腔66a之上的电介质中，器件材料从该空腔中被去除。

5. 发明授权

US06211056B1 Integrated circuit air bridge structures and methods of fabricating same 有权
标题翻译：集成电路空气桥结构及其制造方法
公开(公告)号：US06211056B1
公开(公告)日：2001-04-03
申请号：US09199292
申请日：1998-11-24
申请人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
发明人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
IPC分类号： H01L214763
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5221 , H01L2924/0002 , H01L2924/00
摘要： Conductive elements which provide interconnections (air bridges between circuits) and components such as capacitors and inductors may be incorporated in the devices in a manner to reduce parasitic effects in the operation of the devices while providing close spacing which enhances the performance of the devices at high frequency. Separate substrates are provided respectively having the integrated circuits formed therein and covering, preferably sealing the integrated circuits. The air bridge conductive components (interconnections, capacitors or inductors) are formed separately in the covering substrate which is assembled with the substrate having the integrated circuit as a lid which seals and packages the circuits and the conductive element or component contained in the lid. The conductive component may be separated by cavities formed in the lid substrate or in the substrate having the integrated circuit device already formed therein. Assembly may take place at temperatures lower than necessary for fusion bonding and diffusion commonly used in the fabrication of integrated circuits. Bonds which are used may be metal, oxide or plastic (polymer) bonding material.
摘要翻译：提供互连（电路之间的空气桥）和诸如电容器和电感器的部件的导电元件可以以减少器件操作中的寄生效应的方式并入器件中，同时提供紧密的间隔，这增强了器件在高处的性能频率。分别提供分离的基板，其中形成有集成电路并覆盖，优选地密封集成电路。空气桥导电部件（互连，电容器或电感器）分别形成在与具有集成电路的基板组装的覆盖基板上，该基板具有密封并封装电路和包含在盖中的导电元件或部件的盖。导电部件可以由形成在盖基板中的空腔或已经形成有集成电路器件的基板分离。组装可能发生在集成电路制造中常用的熔接和扩散所需的温度以下。使用的债券可以是金属，氧化物或塑料（聚合物）结合材料。

6. 发明授权

US5081063A Method of making edge-connected integrated circuit structure 失效
标题翻译：制造边缘连接集成电路结构的方法
公开(公告)号：US5081063A
公开(公告)日：1992-01-14
申请号：US382388
申请日：1989-07-20
申请人： Nicolaas V. Vonno , Patrick A. Begley
发明人： Nicolaas V. Vonno , Patrick A. Begley
IPC分类号： H01L25/065 , H01L27/146
CPC分类号： H01L25/0657 , H01L27/1465 , H01L2224/48091 , H01L2224/48227 , H01L2224/49112 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06596
摘要： A focal plane array and an associated technique for manufacturing such an array, employ a first, substantially planar semiconductor substrate, that contains a densely compacted array of photodiodes, interconnected with a plurality of second semiconductor substrates in which the signal processing electronics for the array are formed. The backside of the focal plane array-containing substrate has an associated array of conductive bumps to which the respective photodiodes on the imaging side are electrically connected. Within plural ones of second semiconductor substrates, each of which is associated with a respective row of the array of photodiodes there are integrated the signal processing electronics for that row. Formed along side edge portions of the second substrates are a plurality of metallic bumps which are conductively connected to the signal processing electronics. Each signal processing substrate is conductively joined to the photodiode chip by corresponding bumps that have been electroplated along the side edge portion of that second semiconductor substrate to internal conductive regions that terminate at that side edge portion. Each conductive region is preferably comprised of doped semiconductor material which extends to the side edge portion of the substrate and is connected to regions of the signal processing devices within the semiconductor substrate.
摘要翻译：焦平面阵列和用于制造这种阵列的相关技术采用第一基本上平面的半导体衬底，其包含密集紧凑的光电二极管阵列，与多个第二半导体衬底互连，其中阵列的信号处理电子器件形成。含焦点平面阵列的衬底的背面具有相关阵列的导电凸块，成像侧上的各个光电二极管与其电连接。在多个第二半导体衬底中，每个第二半导体衬底与光电二极管阵列的相应行相关联，其中集成了用于该行的信号处理电子器件。形成在第二基板的侧边缘部分的是与信号处理电子装置导电连接的多个金属凸块。每个信号处理基板通过已沿着该第二半导体基板的侧边缘部分电镀的相应的凸起导电地接合到光电二极管芯片到终止于该侧边缘部分的内部导电区域。每个导电区域优选地由掺杂的半导体材料组成，该掺杂半导体材料延伸到衬底的侧边缘部分并连接到半导体衬底内的信号处理器件的区域。

7. 发明授权

US5915168A Lid wafer bond packaging and micromachining 失效
标题翻译：盖子晶圆封装和微加工
公开(公告)号：US5915168A
公开(公告)日：1999-06-22
申请号：US73776
申请日：1998-05-06
申请人： Matthew M. Salatino , William R. Young , Patrick A. Begley
发明人： Matthew M. Salatino , William R. Young , Patrick A. Begley
IPC分类号： H01L23/02 , B29C43/36 , B81B3/00 , B81B7/00 , H01L23/04 , H01L23/10 , H01L27/146 , H03H9/05 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： B81C1/00333 , B29C43/36 , H01L23/10 , H01L27/14618 , H03H9/0547 , B29C33/0022 , B81C2203/0109 , B81C2203/0118 , B81C2203/0127 , H01L2924/0002 , H01L2924/01079
摘要： A wafer level hermetically packaged integrated circuit has a protective cover wafer bonded to a semiconductor device substrate wafer. The substrate wafer may contain a cavity. The cover wafer seals integrated circuits and other devices including but not limited to air bridge structures, resonant beams, surface acoustic wave (SAW) devices, trimmable resistors, and micromachines. Some devices, such as SAWs, are formed on the surface of cavities formed in the protective cover wafer. Die are separated to complete the process.
摘要翻译：晶圆级密封的集成电路具有与半导体器件衬底晶片接合的保护盖晶片。衬底晶片可以包含空腔。封装晶片密封集成电路和其他器件，包括但不限于空气桥结构，谐振光束，声表面波（SAW）器件，微调电阻器和微机械。一些器件，例如SAW形成在形成在保护盖晶片中的空腔的表面上。模具分离完成过程。

8. 发明授权

US5798557A Lid wafer bond packaging and micromachining 失效
公开(公告)号：US5798557A
公开(公告)日：1998-08-25
申请号：US705536
申请日：1996-08-29
申请人： Matthew M. Salatino , William R. Young , Patrick A. Begley
发明人： Matthew M. Salatino , William R. Young , Patrick A. Begley
IPC分类号： H01L23/02 , B29C43/36 , B81B3/00 , B81B7/00 , H01L23/04 , H01L23/10 , H01L27/146 , H03H9/05 , H01L29/82
CPC分类号： B81C1/00333 , B29C43/36 , H01L23/10 , H01L27/14618 , H03H9/0547 , B29C33/0022 , B81C2203/0109 , B81C2203/0118 , B81C2203/0127 , H01L2924/0002 , H01L2924/01079
摘要： A wafer level hermetically packaged integrated circuit has a protective cover wafer bonded to a semiconductor device substrate wafer. The substrate wafer may contain a cavity. The cover wafer seals integrated circuits and other devices including but not limited to air bridge structures, resonant beams, surface acoustic wave (SAW) devices, trimmable resistors, and micromachines. Some devices, such as SAWs, are formed on the surface of cavities formed in the protective cover wafer. Die are separated to complete the process.

9. 发明授权

US5773151A Semi-insulating wafer 失效
标题翻译：半绝缘晶圆
公开(公告)号：US5773151A
公开(公告)日：1998-06-30
申请号：US497404
申请日：1995-06-30
申请人： Patrick A. Begley , Anthony Rivoli , Gyorgy Bajor , Rex E. Lowther
发明人： Patrick A. Begley , Anthony Rivoli , Gyorgy Bajor , Rex E. Lowther
IPC分类号： H01L21/762 , B32B9/04
CPC分类号： H01L21/76251
摘要： A bonded wafer 10 has a silicon device layer 20 bonded to a layer of semi-insulating material 14, preferably a mobility degraded silicon such as polycrystaline silicon. Layer 14 is thick enough and substrate 16 is conductive enough to reduce resistive losses when devices in layer 20 are operated at frequencies above 0.1 Ghz. Substrate 16 is conductive enough and semi-insulating material 14 is resistive enough to prevent cross-talk among devices in layer 20.
摘要翻译：键合晶片10具有结合到半绝缘材料层14的硅器件层20，优选迁移率降低的硅，例如多晶硅。层14足够厚，并且当层20中的器件以高于0.1Ghz的频率工作时，衬底16足够导电以减少电阻损耗。基板16是足够导电的，半绝缘材料14具有足够的电阻以防止层20中的器件之间的串扰。

10. 发明授权

US5648678A Programmable element in barrier metal device 失效
标题翻译：阻挡金属器件中的可编程元件
公开(公告)号：US5648678A
公开(公告)日：1997-07-15
申请号：US310280
申请日：1994-09-21
申请人： Patrick A. Begley , John T. Gasner , Lawrence G. Pearce , Choong S. Rhee , Jeanne M. McNamara , John J. Hackenberg , Donald F. Hemmenway
发明人： Patrick A. Begley , John T. Gasner , Lawrence G. Pearce , Choong S. Rhee , Jeanne M. McNamara , John J. Hackenberg , Donald F. Hemmenway
IPC分类号： H01L23/525 , H01L27/102 , H01L29/00
CPC分类号： H01L27/1021 , H01L23/5252 , H01L2924/0002 , Y10S257/926
摘要： An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.
摘要翻译：集成电路10具有可扩展区域18和16以及金属触点34和32的可编程齐纳二极管。阻挡金属30设置在一个触点32和基板12之间; 另一个接触区域18在其表面上没有阻挡金属。多晶硅层22与表面区域18和扩散区域18自对准。硅化物层128可以用在多晶硅层22上和表面区域18上。

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