专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06393554B1 Method and apparatus for performing vector and scalar multiplication and calculating rounded products 有权
标题翻译：执行向量和标量乘法并计算舍入积的方法和装置
公开(公告)号：US06393554B1
公开(公告)日：2002-05-21
申请号：US09487771
申请日：2000-01-19
申请人： Stuart F. Oberman , Ming Siu , Ravi Krishna Cherukuri
发明人： Stuart F. Oberman , Ming Siu , Ravi Krishna Cherukuri
IPC分类号： G06F752
CPC分类号： G06F7/53 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16 , G06F2207/3828
摘要： A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur.
摘要翻译：公开了能够执行有符号和无符号标量和矢量乘法的乘法器。乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。可以基于每个操作数的最高有效位和控制信号来计算乘法器和被乘数操作数的有效符号。然后根据布斯算法，有效符号可用于创建和选择多个部分乘积。一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。结果可能是有符号或无符号的，可能表示向量或标量。当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。最终产品可以以分段输出，以便需要更少的总线。可以通过添加舍入常数来对段进行舍入。可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。

2. 发明授权

US06397239B2 Floating point addition pipeline including extreme value, comparison and accumulate functions 有权
标题翻译：浮点附加流水线包括极值，比较和累加功能
公开(公告)号：US06397239B2
公开(公告)日：2002-05-28
申请号：US09778352
申请日：2001-02-06
申请人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna Cherukuri
发明人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna Cherukuri
IPC分类号： G06F742
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30036 , H03M7/24
摘要： A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.
摘要翻译：多媒体执行单元被配置为执行矢量的浮点和整数指令。执行单元可以包括具有远近数据路径的加法/减法流水线。远程路径被配置为处理具有大于1的绝对指数差的操作数的有效加法运算和有效减法运算。关闭路径被配置为处理具有小于或等于1的绝对指数差的操作数的有效减法操作。关闭路径被配置为生成两个输出值，其中一个输出值是第一输入操作数加上第二输入操作数的反转版本，而第二输出值等于第一输出值加1。在闭合路径中选择第一或第二输出值对加法器的输出实现了舍入到最近的运算。

3. 发明授权

US6026483A Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands 失效
标题翻译：用于同时对两对或更多对操作数执行算术的方法和装置
公开(公告)号：US6026483A
公开(公告)日：2000-02-15
申请号：US014455
申请日：1998-01-28
申请人： Stuart F. Oberman , Ravikrishna Cherukuri , Ming Siu
发明人： Stuart F. Oberman , Ravikrishna Cherukuri , Ming Siu
IPC分类号： G06F7/52 , G06F7/533 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F17/16
CPC分类号： G06F7/53 , G06F17/16 , G06F7/5443 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F2207/3828 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338
摘要： A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, the adder is configured to sum them and output the results, which may be signed or unsigned. When a vector multiplication is performed, the multiplier is configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.
摘要翻译：公开了能够执行有符号和无符号标量和矢量乘法的乘法器。乘法器被配置用于微处理器并且包括部分乘积发生器，选择逻辑单元和加法器。乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。乘法器还被配置为接收指示是否要执行带符号或无符号乘法的第一控制信号，以及指示是否执行向量乘法的第二控制信号。乘法器被配置为基于每个操作数的最高有效位和控制信号来计算乘数的有效符号和被乘数操作数。然后，有效符号可以被部分乘积生成单元和选择逻辑用于根据布斯算法创建和选择多个部分乘积。一旦创建并选择了部分产品，加法器被配置为对它们进行求和并输出结果，这可能是有符号或无符号的。当执行向量乘法时，乘法器被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。

4. 发明授权

US08860737B2 Programmable graphics processor for multithreaded execution of programs 有权
标题翻译：用于多线程执行程序的可编程图形处理器
公开(公告)号：US08860737B2
公开(公告)日：2014-10-14
申请号：US11458633
申请日：2006-07-19
申请人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
发明人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20 , G06T15/00 , G06F12/08 , G06T15/10
CPC分类号： G06T15/005 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06T15/10
摘要： A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
摘要翻译：处理单元包括多个执行流水线，每个执行流水线连接到第一输入部分，用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和用于存储经处理的顶点数据的第二输出部分。经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。经处理的像素数据被输出到光栅分析器。

5. 发明授权

US07834881B2 Operand collector architecture 有权
标题翻译：操作数收集架构
公开(公告)号：US07834881B2
公开(公告)日：2010-11-16
申请号：US11555649
申请日：2006-11-01
申请人： Samuel Liu , John Erik Lindholm , Ming Y Siu , Brett W. Coon , Stuart F. Oberman
发明人： Samuel Liu , John Erik Lindholm , Ming Y Siu , Brett W. Coon , Stuart F. Oberman
IPC分类号： G09G5/36 , G09G5/39 , G06F15/80
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30167 , G06F9/3824 , G06F9/3851 , G06F9/3885
摘要： An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.
摘要翻译：一种使用较低端口计数存储器作为存储体来模拟多端口存储器的装置和方法。收集器单元根据需要从银行收集源操作数，以处理程序指令。收集器单元还收集用作操作数的常量。当收集处理程序指令所需的所有源操作数时，收集器单元将源操作数输出到执行单元，同时避免与由其他执行单元访问的程序指令指定的寄存器的写回冲突。

6. 发明授权

US07042891B2 Dynamic selection of lowest latency path in a network switch 有权
公开(公告)号：US07042891B2
公开(公告)日：2006-05-09
申请号：US09755670
申请日：2001-01-04
申请人： Stuart F. Oberman , Anil Mehta , Rodney N. Mullendore , Kamran Malik
发明人： Stuart F. Oberman , Anil Mehta , Rodney N. Mullendore , Kamran Malik
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： H04L49/25 , H04L49/3018 , H04L49/3027 , H04L49/351
摘要： A system and method for low latency switching of data packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Under normal operation, the data transport logic stores packet data into the memory. Later, the packet data is read from the memory and output to a destination output port. To reduce latency when the switch is not congested, the switching logic may be configured to perform a cut-through operation by routing packets directly from input ports to output ports without storing any portion of the packet in the memory. Alternatively, the switch may begin forwarding the stored packet data to the output port before the entire packet has been received or stored in the memory.

7. 发明授权

US06490607B1 Shared FP and SIMD 3D multiplier 有权
标题翻译：共享FP和SIMD 3D乘数
公开(公告)号：US06490607B1
公开(公告)日：2002-12-03
申请号：US09416401
申请日：1999-10-12
申请人： Stuart F. Oberman
发明人： Stuart F. Oberman
IPC分类号： G06F752
CPC分类号： G06F7/53 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338 , G06F7/5443 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16 , G06F2207/3824 , G06F2207/3828
摘要： A multiplier configured to perform multiplication of both scalar floating point values (X×Y) and packed floating point values (i.e., X1×Y1 and X2×Y2). In addition, the multiplier may be configured to calculate X×Y−Z. The multiplier comprises selection logic for selecting source operands, a partial product generator, an adder tree, and two or more adders configured to sum the results from the adder tree to achieve a final result. The multiplier may also be configured to perform iterative multiplication operations to implement such arithmetical operations such as division and square root. The multiplier may be configured to generate two versions of the final result, one assuming there is an overflow, and another assuming there is not an overflow. A computer system and method for performing multiplication are also disclosed.
摘要翻译：配置为执行两个标量浮点值（XxY）和压缩浮点值（即X1xY1和X2xY2）的乘法的乘法器。此外，乘法器可以被配置为计算XxY-Z。乘法器包括用于选择源操作数的选择逻辑，部分乘积生成器，加法器树和被配置为对来自加法器树的结果求和以获得最终结果的两个或更多个加法器。乘法器还可以被配置为执行迭代乘法运算以实现诸如除法和平方根的算术运算。乘法器可以被配置为生成最终结果的两个版本，一个假设有溢出，另一个假设没有溢出。还公开了一种用于执行乘法的计算机系统和方法。

8. 发明授权

US06298367B1 Floating point addition pipeline including extreme value, comparison and accumulate functions 失效
标题翻译：浮点附加流水线包括极值，比较和累加功能
公开(公告)号：US06298367B1
公开(公告)日：2001-10-02
申请号：US09055916
申请日：1998-04-06
申请人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna
发明人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna
IPC分类号： G06F738
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30036 , H03M7/24
摘要： A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder. The execution unit may be configured to perform vectored addition and subtraction, integer/floating point conversion, reverse subtraction, accumulate, extreme value (minimum/maximum), and comparison instructions.
摘要翻译：多媒体执行单元被配置为执行矢量的浮点和整数指令。执行单元可以包括具有远近数据路径的加法/减法流水线。远程路径被配置为处理具有大于1的绝对指数差的操作数的有效加法运算和有效减法运算。关闭路径被配置为处理具有小于或等于1的绝对指数差的操作数的有效减法操作。关闭路径被配置为生成两个输出值，其中一个输出值是第一输入操作数加上第二输入操作数的反转版本，而第二输出值等于第一输出值加1。在闭合路径中选择第一或第二输出值对加法器的输出实现了舍入到最近的运算。执行单元可以被配置为执行向量加法和减法，整数/浮点转换，反向减法，累加，极值（最小/最大）和比较指令。

9. 发明授权

US06223192B1 Bipartite look-up table with output values having minimized absolute error 失效
标题翻译：输出值为绝对误差最小的双向查找表
公开(公告)号：US06223192B1
公开(公告)日：2001-04-24
申请号：US09098482
申请日：1998-06-16
申请人： Stuart F. Oberman , Norbert Juffa
发明人： Stuart F. Oberman , Norbert Juffa
IPC分类号： G06F102
CPC分类号： G06F7/53 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16 , G06F2207/3828 , H03M7/24
摘要： A method for generating entries for a bipartite look-up table having base and difference table portions. In one embodiment, these entries are usable to form output values for a mathematical function, f(x), in response to receiving corresponding input values within a predetermined input range. The method first comprises partitioning the input range into I intervals, J subintervals/interval, and K sub-subintervals/subinterval. For a given interval M, the method includes generating K difference table entries and J base table entries. Each of the K difference table entries corresponds to a particular group of sub-subintervals within interval M, each of which has the same relative position within their respective subintervals. Each difference table entry is computed by averaging difference values for the sub-subintervals included in a corresponding group N. Each difference value which makes up this average is equal to f(X1)−f(X2), where X1 is the midpoint of the sub-subinterval within group N, and X2 is the midpoint of a predetermined reference sub-subinterval within the same subinterval as X1. Each of these midpoints is calculated such that maximum absolute error is minimized for all possible input values in the sub-subinterval. Each of the J base table entries, on the other hand, corresponds to a subinterval within interval M. Each entry is equal to f(X2)+adjust, where X2 is the midpoint of the reference sub-subinterval of the subinterval corresponding to the base table entry. The adjust value is calculated so that error introduced by the averaging of the difference table entries is evenly distributed over the entire subinterval.
摘要翻译：一种用于为具有基准和差分表部分的二分查找表生成条目的方法。在一个实施例中，响应于在预定输入范围内接收对应的输入值，这些条目可用于形成数学函数f（x）的输出值。该方法首先包括将输入范围分为I个间隔，J个子间隔/间隔和K个子间隔/子间隔。对于给定的间隔M，该方法包括生成K个差表表项和J个基表项。 K个差异表条目中的每一个对应于间隔M内的特定的子子区间组，每个子区间在它们各自的子区间内具有相同的相对位置。通过对包括在对应组N中的子子间隔的差分值进行平均来计算每个差分表项。构成该平均值的每个差值等于f（X1）-f（X2），其中X1是在组N内的子子间隔，X2是与X1相同的子间隔内的预定参考子子间隔的中点。计算这些中点中的每一个，使得对子子区间中的所有可能输入值的最大绝对误差最小化。另一方面，每个J基表条目对应于间隔M内的子间隔。每个条目等于f（X2）+调整，其中X2是对应于子帧的子间隔的参考子子间隔的中点基表项。计算调整值，使得通过差表表项的平均引入的误差在整个子间隔上均匀分布。

10. 发明授权

US6115733A Method and apparatus for calculating reciprocals and reciprocal square roots 失效
标题翻译：用于计算倒数和倒数平方根的方法和装置
公开(公告)号：US6115733A
公开(公告)日：2000-09-05
申请号：US74826
申请日：1998-05-08
申请人： Stuart F. Oberman , Norbert Juffa , Fred Weber
发明人： Stuart F. Oberman , Norbert Juffa , Fred Weber
IPC分类号： G06F7/50 , G06F7/52 , G06F7/533 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F17/16 , H03M7/24 , G06F7/552
CPC分类号： G06F7/53 , G06F17/16 , G06F7/509 , G06F7/5443 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , H03M7/24 , G06F2207/3828 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338
摘要： A processor capable of efficiently evaluating constant powers of an operand such as the reciprocal and reciprocal square root is disclosed. The processor comprises a multiplier that is configured to perform iterative multiplication operations to evaluate constant powers of an operand such as the reciprocal and reciprocal square root. Intermediate products that are formed may be rounded and normalized in two paths, one assuming an overflow will occur, and then compressed and stored for use in the next iteration. The processor comprises a multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier may performing rounded by adding a rounding constant.
摘要翻译：公开了一种能够有效地评估诸如倒数和倒数平方根之类的操作数的恒定功率的处理器。处理器包括乘法器，其被配置为执行迭代乘法运算以评估诸如倒数和倒数平方根的操作数的恒定功率。形成的中间产品可以在两个路径中进行舍入和归一化，一个假定将发生溢出，然后压缩并存储以供下一次迭代使用。该处理器包括能够执行有符号和无符号标量和向量乘法的乘法器。乘法器可以通过添加舍入常数进行舍入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式