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1. 发明授权

US07283556B2 Method and system for managing time division multiplexing (TDM) timeslots in a network switch 失效
标题翻译：用于管理网络交换机中的时分复用（TDM）时隙的方法和系统
公开(公告)号：US07283556B2
公开(公告)日：2007-10-16
申请号：US10209158
申请日：2002-07-31
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/43
CPC分类号： H04L49/103 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/357 , H04Q11/04 , H04Q2213/13292 , H04Q2213/13296 , H04Q2213/13332 , H04Q2213/13389
摘要： A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e.g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.
摘要翻译：一种用于管理网络交换机中时分多路复用（TDM）时隙分配的系统和方法。网络交换机可以使用包括多个时隙的TDM周期来管理共享资源，并且通过当前配置的端口来调度数据入口和出口，其中每个端口被分配一个或多个时隙。网络交换机可以被重新编程以支持多个端口配置之一的多个时隙分配方案之一。网络交换机可以支持具有不同数量端口的配置，例如， 8和16端口配置。网络交换机还可以支持将两个或多个端口组合以形成一个端口（例如，2Gbs光纤通道端口）的配置。为了满足各种配置的要求，时隙分配方案可以被重新编程以满足每个可能的端口配置的调度要求。

2. 发明授权

US07042891B2 Dynamic selection of lowest latency path in a network switch 有权
公开(公告)号：US07042891B2
公开(公告)日：2006-05-09
申请号：US09755670
申请日：2001-01-04
申请人： Stuart F. Oberman , Anil Mehta , Rodney N. Mullendore , Kamran Malik
发明人： Stuart F. Oberman , Anil Mehta , Rodney N. Mullendore , Kamran Malik
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： H04L49/25 , H04L49/3018 , H04L49/3027 , H04L49/351
摘要： A system and method for low latency switching of data packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Under normal operation, the data transport logic stores packet data into the memory. Later, the packet data is read from the memory and output to a destination output port. To reduce latency when the switch is not congested, the switching logic may be configured to perform a cut-through operation by routing packets directly from input ports to output ports without storing any portion of the packet in the memory. Alternatively, the switch may begin forwarding the stored packet data to the output port before the entire packet has been received or stored in the memory.

3. 发明授权

US07406041B2 System and method for late-dropping packets in a network switch 失效
标题翻译：在网络交换机中丢包的系统和方法
公开(公告)号：US07406041B2
公开(公告)日：2008-07-29
申请号：US10209545
申请日：2002-07-31
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/26
CPC分类号： H04L47/30 , H04L47/10 , H04L47/2441 , H04L47/31 , H04L47/32 , H04L49/50
摘要： A system and method for late-dropping packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the switch may be subject to input thresholding, and may be assigned to a flow within a group. A portion of a packet subject to input thresholding may be accepted into the switch and assigned to a group and flow even if, at the time of arrival of the portion, there are not enough resources available to receive the remainder of the packet. This partial receipt of the packet is allowed because of the possibility of additional resources becoming available between the time of receipt of and resource allocation for the portion of the packet and receipt of subsequent portions of the packet.
摘要翻译：一种用于在网络交换机中后期丢包的系统和方法。网络交换机可以包括多个输入端口，多个输出端口以及通过数据传输逻辑耦合到输入端口和输出端口的共享随机存取存储器。进入交换机的数据包可能需要输入阈值，并且可以分配给组内的流。即使在部分到达时，没有足够的资源可用于接收分组的其余部分，经过输入阈值处理的分组的一部分也可被接收到交换机中并分配给组和流。允许分组的这种部分接收是因为在分组的接收时间和分组的部分和分组的后续部分的接收之间有额外的资源可用。

4. 发明授权

US07809852B2 High jitter scheduling of interleaved frames in an arbitrated loop 失效
标题翻译：仲裁循环中交错帧的高抖动调度
公开(公告)号：US07809852B2
公开(公告)日：2010-10-05
申请号：US10152763
申请日：2002-05-22
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： G06F13/00
CPC分类号： H04L47/6215 , H04L12/433 , H04L47/22 , H04L47/283 , H04L47/50 , H04L47/6225 , H04L49/357
摘要： A system and method for converting low-jitter, interleaved frame traffic, such as that generated in an IP network, to high jitter traffic to improve the utilization of bandwidth on arbitrated loops such as Fibre Channel Arbitrated Loops. Embodiments of a high jitter scheduling algorithm may be used in devices such as network switches that interface an arbitrated loop with an IP network that carries low-jitter traffic. The high jitter algorithm may use a separate queue for each device on the arbitrated loop, or alternatively may use one queue for two or more devices. Incoming frames are distributed among the queues based upon each frame's destination device. The scheduling algorithm may then service the queues and forward queued frames to the devices from the queues. In one embodiment, the queues are serviced in a round-robin fashion. In one embodiment, each queue may be serviced for a programmed limit.
摘要翻译：将诸如IP网络中生成的低抖动交织帧流量转换为高抖动流量以提高诸如光纤通道仲裁环路之类的仲裁环路上的带宽利用率的系统和方法。高抖动调度算法的实施例可以用于诸如将仲裁环路与承载低抖动流量的IP网络相连接的网络交换机的设备。高抖动算法可以对仲裁环路上的每个设备使用单独的队列，或者可以为两个或更多个设备使用一个队列。基于每个帧的目的地设备，进入的帧被分配在队列之间。然后，调度算法可以对队列进行服务并将排队的帧从队列转发到设备。在一个实施例中，队列以循环方式服务。在一个实施例中，每个队列可以被服务于编程限制。

5. 发明授权

US07227841B2 Packet input thresholding for resource distribution in a network switch 失效
标题翻译：网络交换机资源分配的分组输入阈值
公开(公告)号：US07227841B2
公开(公告)日：2007-06-05
申请号：US10144081
申请日：2002-05-13
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： G01R31/08
CPC分类号： H04L47/32 , H04L47/29 , H04L47/50 , H04L49/103 , H04L49/108 , H04L49/30 , H04L49/90 , H04L49/901 , H04L49/9036 , H04L49/9094 , H04L2012/5681
摘要： A system and method for input thresholding packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the network switch may be assigned to one of a plurality of threshold groups and to one of a plurality of flows within the threshold group. In one embodiment, each threshold group may be divided into a plurality of levels of operation. As resources are allocated or freed by the threshold group, the threshold group may dynamically move up or down in the levels of operation. Within each level, one or more different values may be used as level boundaries and resource limits for flows within the threshold group. In one embodiment, programmable registers may be used to store these values.
摘要翻译：一种用于在网络交换机中输入阈值分组的系统和方法。网络交换机可以包括多个输入端口，多个输出端口以及通过数据传输逻辑耦合到输入端口和输出端口的共享随机存取存储器。可以将进入网络交换机的分组分配给多个阈值组中的一个和阈值组内的多个流中的一个。在一个实施例中，每个阈值组可被划分成多个操作级别。当资源由阈值组分配或释放时，阈值组可以在操作级别上动态上移或下移。在每个级别内，可以使用一个或多个不同的值作为阈值组内的流的级别边界和资源限制。在一个实施例中，可以使用可编程寄存器来存储这些值。

6. 发明授权

US07215680B2 Method and apparatus for scheduling packet flow on a fibre channel arbitrated loop 失效
标题翻译：用于在光纤信道仲裁环路上调度分组流的方法和装置
公开(公告)号：US07215680B2
公开(公告)日：2007-05-08
申请号：US10144187
申请日：2002-05-13
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/56
CPC分类号： H04L47/2433 , H04L47/50 , H04L47/56 , H04L47/6225 , H04L49/205 , H04L49/254 , H04L49/3018 , H04L49/351 , H04L49/357 , H04L67/1097 , H04L69/329
摘要： A system and method for enabling a network switch to transmit queued packets to a device when opened by the device, and thus to utilize the Fibre Channel Arbitrated Loop (FC-AL) in full-duplex mode when possible. The switch may include a plurality of queues each associated with a device on the FC-AL for queuing incoming packets for the device. The switch may determine a next non-empty queue, open the device associated with the queue, and send packets to the device. The device may send packets to the switch concurrently with receiving packets from the switch, thus utilizing the FC-AL in full-duplex mode. When a device opens the switch to transmit packets to the switch, the switch may determine if there are packets for the device in the queue and, if so, send packets to the device concurrently with receiving packets from the device, thus utilizing the FC-AL in full-duplex mode.
摘要翻译：一种用于使网络交换机能够在设备打开时将排队的分组传送到设备的系统和方法，并且因此在可能的情况下以全双工模式利用光纤通道仲裁环路（FC-AL）。交换机可以包括多个队列，每个队列与FC-AL上的设备相关联，用于对用于设备的输入分组进行排队。交换机可以确定下一个非空队列，打开与队列关联的设备，并将数据包发送到设备。设备可以同时从交换机接收数据包发送数据包，从而在全双工模式下利用FC-AL。当设备打开交换机向交换机发送数据包时，交换机可以确定队列中是否存在设备的数据包，如果是，则从设备接收数据包并发发送数据包，从而利用FC- AL在全双工模式。

7. 发明申请

US20080080548A1 Method and System for Managing Time Division Multiplexing (TDM) Timeslots in a Network Switch 审中-公开
标题翻译：用于管理网络交换机中的时分复用（TDM）时隙的方法和系统
公开(公告)号：US20080080548A1
公开(公告)日：2008-04-03
申请号：US11871105
申请日：2007-10-11
申请人： Rodney Mullendore , Stuart Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney Mullendore , Stuart Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04B7/212
CPC分类号： H04L49/103 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/357 , H04Q11/04 , H04Q2213/13292 , H04Q2213/13296 , H04Q2213/13332 , H04Q2213/13389
摘要： A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e.g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.
摘要翻译：一种用于管理网络交换机中时分多路复用（TDM）时隙分配的系统和方法。网络交换机可以使用包括多个时隙的TDM周期来管理共享资源，并且通过当前配置的端口来调度数据入口和出口，其中每个端口被分配一个或多个时隙。网络交换机可以被重新编程以支持多个端口配置之一的多个时隙分配方案之一。网络交换机可以支持具有不同数量端口的配置，例如， 8和16端口配置。网络交换机还可以支持将两个或多个端口组合以形成一个端口（例如，2Gbs光纤通道端口）的配置。为了满足各种配置的要求，时隙分配方案可以被重新编程以满足每个可能的端口配置的调度要求。

8. 发明授权

US06308252B1 Processor method and apparatus for performing single operand operation and multiple parallel operand operation 有权
标题翻译：用于执行单操作数操作和多个并行操作数操作的处理器方法和装置
公开(公告)号：US06308252B1
公开(公告)日：2001-10-23
申请号：US09244443
申请日：1999-02-04
申请人： Rakesh Agarwal , Kamran Malik , Tatsuo Teruyama
发明人： Rakesh Agarwal , Kamran Malik , Tatsuo Teruyama
IPC分类号： G06F1580
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3824 , G06F9/3836 , G06F9/3887 , G06F9/3889 , G06F15/8007
摘要： A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e.g., 64-bit) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m
摘要翻译：处理器包括用于保持指令操作数的n位（例如，128位）寄存器电路。指令解码电路从指令流解码处理器指令。算术逻辑（AL）电路可操作以对从n位寄存器电路提供的至少一个m位最大值（例如，64位）操作数执行单个操作中的一个操作，响应于由指令解码电路，其中m

9. 发明授权

US06412057B1 Microprocessor with virtual-to-physical address translation using flags 失效
标题翻译：使用标志的虚拟到物理地址转换的微处理器
公开(公告)号：US06412057B1
公开(公告)日：2002-06-25
申请号：US09246407
申请日：1999-02-08
申请人： Masashi Sasahara , Rakesh Agarwal , Kamran Malik , Michael Raam
发明人： Masashi Sasahara , Rakesh Agarwal , Kamran Malik , Michael Raam
IPC分类号： G06F1200
CPC分类号： G06F12/10 , G06F12/1054
摘要： A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.
摘要翻译：微处理器包括从虚拟地址转换为物理地址的MMU以及控制加载/存储指令的执行的LSU。 LSU包括临时存储从外部存储器读出并写入外部存储器的数据的DCACHE，用于除了高速缓存之外的特定用途的SPRAM以及生成用于访问DCACHE和SPRAM的虚拟地址的地址生成器。 MMU生成一个转换表，执行从虚拟地址到物理地址的转换。表示是否执行对SPRAM的访问的标志信息被包括在该转换表中。如果标志被设置，LSU绝对访问SPRAM。因此，不需要将SPRAM分配给主存储器的存储器映射，并且简化了存储器映射的分配。

10. 发明授权

US06389527B1 Microprocessor allowing simultaneous instruction execution and DMA transfer 有权
标题翻译：微处理器允许同时执行指令和DMA传输
公开(公告)号：US06389527B1
公开(公告)日：2002-05-14
申请号：US09246406
申请日：1999-02-08
申请人： Michael Raam , Toru Utsumi , Takeki Osanai , Kamran Malik
发明人： Michael Raam , Toru Utsumi , Takeki Osanai , Kamran Malik
IPC分类号： G06F1500
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/0888
摘要： The present invention comprises a LSU which executes instructions relating to load/store. The LSU includes a DCACHE which temporarily stores data read from and written to the external memory, an SPRAM used to specific purposes other than cache, and an address generator generating virtual addresses for access to the DCACHE and the SPRAM. Because the SPRAM can load and store data by a pipeline of the LSU and exchanges data with an external memory through a DMA transfer, the present invention is especially available to high-speedily process a large amount of data such as the image data. Because the LSU can access the SPRAM with the same latency as that of the DCACHE, after data being stored in the external memory is transferred to the SPRAM, the processor can access the SPRAM in order to perform data process, and it is possible to process a large amount of data with shorter time than time necessary to directly access an external memory.
摘要翻译：本发明包括执行与加载/存储相关的指令的LSU。 LSU包括临时存储从外部存储器读取并写入外部存储器的数据的DCACHE，用于除缓存之外的特定目的的SPRAM以及生成用于访问DCACHE和SPRAM的虚拟地址的地址生成器。因为SPRAM可以通过LSU的流水线加载和存储数据，并且通过DMA传输与外部存储器交换数据，所以本发明特别可用于高速处理诸如图像数据的大量数据。由于LSU可以以与DCACHE相同的延迟访问SPRAM，因此在将存储在外部存储器中的数据传输到SPRAM之后，处理器可以访问SPRAM以执行数据处理，并且可以处理大量数据的时间短于直接访问外部存储器所需的时间。

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