专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08392757B2 Method and apparatus for processing load instructions in a microprocessor having an enhanced instruction decoder and an enhanced load store unit 有权
标题翻译：用于处理具有增强指令解码器和增强型加载存储单元的微处理器中的加载指令的方法和装置
公开(公告)号：US08392757B2
公开(公告)日：2013-03-05
申请号：US12910136
申请日：2010-10-22
申请人： Krishnan Ramani , Mike Butler , Kai Troester
发明人： Krishnan Ramani , Mike Butler , Kai Troester
IPC分类号： G06F11/00
CPC分类号： G06F11/076 , G06F9/3834 , G06F9/3838 , G06F9/3861
摘要： A method and microprocessor are described for efficiently executing load instructions out-of-order (speculatively). The microprocessor includes an enhanced load store unit (LSU) and an enhanced instruction decoder. The enhanced LSU receives a plurality of out-of-order value addresses, and sends a resync signal to the enhanced instruction decoder when an execution error associated with a particular load instruction occurs. The enhanced instruction decoder stores a specific address associated with the particular load instruction, and increments a counter value that indicates how many times the resync signal was sent by the resync predictor. When the counter value reaches a predetermined threshold, subsequent load instructions from the specific address are executed in order (non-speculatively). When a future execution of the particular load instruction indicates that the probability of an execution error has been reduced, the counter value is decremented, facilitating newer load instructions associated with the same address to again be executed speculatively.
摘要翻译：描述了一种方法和微处理器，用于有效地执行无序（推测）的加载指令。微处理器包括增强型加载存储单元（LSU）和增强型指令译码器。增强的LSU接收多个无序值地址，并且当与特定加载指令相关联的执行错误发生时，向增强型指令解码器发送重新同步信号。增强指令解码器存储与特定加载指令相关联的特定地址，并且增加指示再同步预测器发送重新同步信号的次数的计数器值。当计数器值达到预定阈值时，来自特定地址的后续加载指令按顺序（非推测性地）执行。当特定加载指令的将来执行指示执行错误的概率已经减小时，计数器值减少，便于与相同地址相关联的较新加载指令再次被推测地执行。

2. 发明授权

US07822951B2 System and method of load-store forwarding 有权
标题翻译：加载存储转发的系统和方法
公开(公告)号：US07822951B2
公开(公告)日：2010-10-26
申请号：US11832303
申请日：2007-08-01
申请人： Krishnan Ramani , Gary Lauterbach
发明人： Krishnan Ramani , Gary Lauterbach
IPC分类号： G06F9/38
CPC分类号： G06F9/3834
摘要： A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted store addresses or if the forwarding fails during the first pass due to any other reason. In a first pass, the youngest store instruction in program order of all store instructions older than a load instruction is found and an indication to the store buffer entry holding information of the youngest store instruction is recorded. In a second pass, the recorded indication is used to index the store buffer and the store bypass data is forwarded to the load instruction. Simultaneously, it is verified if no new store, younger than the previously identified store and older than the load has not been issued due to out-of-order execution.
摘要翻译：当加载指令地址与多个较旧的未提交的存储地址匹配时，或者由于任何其他原因在第一次通过期间转发失败时，用于在无序执行期间从存储指令到加载指令的数据转发的系统和方法。在第一次通过中，找到比加载指令更早的所有存储指令的程序顺序中最年轻的存储指令，并且记录对最小存储指令的存储缓冲器条目保存信息的指示。在第二遍中，记录的指示用于索引存储缓冲器，并且存储旁路数据被转发到加载指令。同时，验证是否由于无序执行而没有发布比先前识别的商店更旧的负载的新商店。

3. 发明申请

US20120137109A1 METHOD AND APPARATUS FOR PERFORMING STORE-TO-LOAD FORWARDING FROM AN INTERLOCKING STORE USING AN ENHANCED LOAD/STORE UNIT IN A PROCESSOR 有权
标题翻译：使用处理器中的增强负载/存储单元从互连存储进行存储负载转发的方法和装置
公开(公告)号：US20120137109A1
公开(公告)日：2012-05-31
申请号：US12956299
申请日：2010-11-30
申请人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
发明人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3826
摘要： A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.
摘要翻译：描述了一种从联锁商店执行存储到负载转发（STLF）的方法和处理器加载/存储单元（LSU）。当存储的起始地址和负载不匹配时，或者当存储的数据大小小于负载的数据大小时，执行STLF。 LSU检测与存储互锁的负载，并且确定负载所需的全部或仅一部分数据字节可以由联锁存储提供。如果确定只能通过联锁存储器提供负载所需的数据字节的一部分，则该部分数据字节由存储数据缓冲器（SDB）提供，并且数据字节的剩余部分需要由负载由数据缓存（DC）提供。否则，SDB提供所有数据字节。

4. 发明申请

US20050247774A1 System and method for validating a memory file that links speculative results of load operations to register values 有权
标题翻译：用于验证将加载操作的推测结果链接到寄存器值的存储器文件的系统和方法
公开(公告)号：US20050247774A1
公开(公告)日：2005-11-10
申请号：US10839474
申请日：2004-05-05
申请人： Benjamin Sander , Krishnan Ramani , Ramsey Haddad , Mitchell Alsup
发明人： Benjamin Sander , Krishnan Ramani , Ramsey Haddad , Mitchell Alsup
IPC分类号： G06F9/34 , G06F9/38 , G06F17/00
CPC分类号： G06F9/3842 , G06F9/3826 , G06F9/383 , G06F9/3832 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： A system and method for linking speculative results of load operations to register values. A system includes a memory file including an entry configured to store a first addressing pattern and a first tag. The memory file is configured to compare the first addressing pattern to a second addressing pattern of a load operation, and to link a data value identified by the first tag to a speculative result of the load operation if there is a match. The system further includes an execution core coupled to the memory file and configured to access the speculative result when executing a second operation that is dependent on the load operation, and a load store unit coupled to the memory file and configured to verify the link between the data value and the speculative result of the load operation by performing a comparison between one or more addresses.
摘要翻译：一种用于将加载操作的推测结果与寄存器值相关联的系统和方法。系统包括存储器文件，其包括被配置为存储第一寻址模式和第一标签的条目。存储器文件被配置为将第一寻址模式与加载操作的第二寻址模式进行比较，并且如果存在匹配，则将由第一标签识别的数据值链接到加载操作的推测结果。所述系统还包括耦合到所述存储器文件并且被配置为在执行取决于所述加载操作的第二操作时访问所述推测结果的执行核心，以及耦合到所述存储器文件并被配置为验证所述数据值和通过执行一个或多个地址之间的比较的加载操作的推测结果。

5. 发明授权

US06397239B2 Floating point addition pipeline including extreme value, comparison and accumulate functions 有权
标题翻译：浮点附加流水线包括极值，比较和累加功能
公开(公告)号：US06397239B2
公开(公告)日：2002-05-28
申请号：US09778352
申请日：2001-02-06
申请人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna Cherukuri
发明人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna Cherukuri
IPC分类号： G06F742
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30036 , H03M7/24
摘要： A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.
摘要翻译：多媒体执行单元被配置为执行矢量的浮点和整数指令。执行单元可以包括具有远近数据路径的加法/减法流水线。远程路径被配置为处理具有大于1的绝对指数差的操作数的有效加法运算和有效减法运算。关闭路径被配置为处理具有小于或等于1的绝对指数差的操作数的有效减法操作。关闭路径被配置为生成两个输出值，其中一个输出值是第一输入操作数加上第二输入操作数的反转版本，而第二输出值等于第一输出值加1。在闭合路径中选择第一或第二输出值对加法器的输出实现了舍入到最近的运算。

6. 发明申请

US20090037697A1 SYSTEM AND METHOD OF LOAD-STORE FORWARDING 有权
标题翻译：负载存储的系统和方法
公开(公告)号：US20090037697A1
公开(公告)日：2009-02-05
申请号：US11832303
申请日：2007-08-01
申请人： Krishnan Ramani , Gary Lauterbach
发明人： Krishnan Ramani , Gary Lauterbach
IPC分类号： G06F9/30
CPC分类号： G06F9/3834
摘要： A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted store addresses or if the forwarding fails during the first pass due to any other reason. In a first pass, the youngest store instruction in program order of all store instructions older than a load instruction is found and an indication to the store buffer entry holding information of the youngest store instruction is recorded. In a second pass, the recorded indication is used to index the store buffer and the store bypass data is forwarded to the load instruction. Simultaneously, it is verified if no new store, younger than the previously identified store and older than the load has not been issued due to out-of-order execution.
摘要翻译：当加载指令地址与多个较旧的未提交的存储地址匹配时，或者由于任何其他原因在第一次通过期间转发失败时，用于在无序执行期间从存储指令到加载指令的数据转发的系统和方法。在第一次通过中，找到比加载指令更早的所有存储指令的程序顺序中最年轻的存储指令，并且记录对最小存储指令的存储缓冲器条目保存信息的指示。在第二遍中，记录的指示用于索引存储缓冲器，并且存储旁路数据被转发到加载指令。同时，验证是否由于无序执行而没有发布比先前识别的商店更旧的负载的新商店。

7. 发明授权

US08683179B2 Method and apparatus for performing store-to-load forwarding from an interlocking store using an enhanced load/store unit in a processor 有权
标题翻译：用于使用处理器中的增强的加载/存储单元从联锁商店执行存储到负载转发的方法和装置
公开(公告)号：US08683179B2
公开(公告)日：2014-03-25
申请号：US12956299
申请日：2010-11-30
申请人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
发明人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834 , G06F9/3826
摘要： A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.
摘要翻译：描述了一种从联锁商店执行存储到负载转发（STLF）的方法和处理器加载/存储单元（LSU）。当存储的起始地址和负载不匹配时，或者当存储的数据大小小于负载的数据大小时，执行STLF。 LSU检测与存储互锁的负载，并且确定负载所需的全部或仅一部分数据字节可以由联锁存储提供。如果确定只能通过联锁存储器提供负载所需的一部分数据字节，则该部分数据字节由存储数据缓冲器（SDB）提供，并且数据字节的剩余部分需要由负载由数据缓存（DC）提供。否则，SDB提供所有数据字节。

8. 发明申请

US20120102357A1 METHOD AND APPARATUS FOR PROCESSING LOAD INSTRUCTIONS IN A MICROPROCESSOR HAVING AN ENHANCED INSTRUCTION DECODER AND AN ENHANCED LOAD STORE UNIT 有权
标题翻译：在具有加强指令解码器和增强型加载存储单元的微处理器中处理负载指令的方法和装置
公开(公告)号：US20120102357A1
公开(公告)日：2012-04-26
申请号：US12910136
申请日：2010-10-22
申请人： Krishnan Ramani , Mike Butler , Kai Troester
发明人： Krishnan Ramani , Mike Butler , Kai Troester
IPC分类号： G06F11/07
CPC分类号： G06F11/076 , G06F9/3834 , G06F9/3838 , G06F9/3861
摘要： A method and microprocessor are described for efficiently executing load instructions out-of-order (speculatively). The microprocessor includes an enhanced load store unit (LSU) and an enhanced instruction decoder. The enhanced LSU receives a plurality of out-of-order value addresses, and sends a resync signal to the enhanced instruction decoder when an execution error associated with a particular load instruction occurs. The enhanced instruction decoder stores a specific address associated with the particular load instruction, and increments a counter value that indicates how many times the resync signal was sent by the resync predictor. When the counter value reaches a predetermined threshold, subsequent load instructions from the specific address are executed in order (non-speculatively). When a future execution of the particular load instruction indicates that the probability of an execution error has been reduced, the counter value is decremented, facilitating newer load instructions associated with the same address to again be executed speculatively.
摘要翻译：描述了一种方法和微处理器，用于有效地执行无序（推测）的加载指令。微处理器包括增强型加载存储单元（LSU）和增强型指令译码器。增强的LSU接收多个无序值地址，并且当与特定加载指令相关联的执行错误发生时，向增强型指令解码器发送重新同步信号。增强指令解码器存储与特定加载指令相关联的特定地址，并且增加指示再同步预测器发送重新同步信号的次数的计数器值。当计数器值达到预定阈值时，来自特定地址的后续加载指令按顺序（非推测性地）执行。当特定加载指令的将来执行指示执行错误的概率已经减小时，计数器值减少，便于与相同地址相关联的较新加载指令再次被推测地执行。

9. 发明授权

US06298367B1 Floating point addition pipeline including extreme value, comparison and accumulate functions 失效
标题翻译：浮点附加流水线包括极值，比较和累加功能
公开(公告)号：US06298367B1
公开(公告)日：2001-10-02
申请号：US09055916
申请日：1998-04-06
申请人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna
发明人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna
IPC分类号： G06F738
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30036 , H03M7/24
摘要： A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder. The execution unit may be configured to perform vectored addition and subtraction, integer/floating point conversion, reverse subtraction, accumulate, extreme value (minimum/maximum), and comparison instructions.
摘要翻译：多媒体执行单元被配置为执行矢量的浮点和整数指令。执行单元可以包括具有远近数据路径的加法/减法流水线。远程路径被配置为处理具有大于1的绝对指数差的操作数的有效加法运算和有效减法运算。关闭路径被配置为处理具有小于或等于1的绝对指数差的操作数的有效减法操作。关闭路径被配置为生成两个输出值，其中一个输出值是第一输入操作数加上第二输入操作数的反转版本，而第二输出值等于第一输出值加1。在闭合路径中选择第一或第二输出值对加法器的输出实现了舍入到最近的运算。执行单元可以被配置为执行向量加法和减法，整数/浮点转换，反向减法，累加，极值（最小/最大）和比较指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式