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1. 发明授权

US08954485B2 Range check based lookup tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US08954485B2
公开(公告)日：2015-02-10
申请号：US13608189
申请日：2012-09-10
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/38 , G06F7/44
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路将第二值与边界单元值子集中的每个边界单元值进行比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

2. 发明申请

US20130173681A1 Range Check Based Lookup Tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US20130173681A1
公开(公告)日：2013-07-04
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F1/035 , G06F12/00 , G06F7/487
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路对边界单元值子集中的每个边界单元值进行第二值的比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

3. 发明授权

US08914431B2 Range check based lookup tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US08914431B2
公开(公告)日：2014-12-16
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路将第二值与边界单元值子集中的每个边界单元值进行比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

4. 发明申请

US20130173683A1 Range Check Based Lookup Tables 有权
公开(公告)号：US20130173683A1
公开(公告)日：2013-07-04
申请号：US13608189
申请日：2012-09-10
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/535 , G06F12/00
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

5. 发明申请

US20110320512A1 Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection 失效
标题翻译：十进制浮点机制和乘法过程，无需导致零检测
公开(公告)号：US20110320512A1
公开(公告)日：2011-12-29
申请号：US12821648
申请日：2010-06-23
申请人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
发明人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
IPC分类号： G06F7/44 , G06F5/01
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.
摘要翻译：具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假设最终产品的长度为M + N个数字，并且基于该假设执行所有计算。将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。如果后者是真实的，则采用校正最终产品转换来获得适当的结果。这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。

6. 发明授权

US08495124B2 Decimal floating point mechanism and process of multiplication without resultant leading zero detection 失效
标题翻译：十进制浮点机制和乘法处理，而没有得到前导零检测
公开(公告)号：US08495124B2
公开(公告)日：2013-07-23
申请号：US12821648
申请日：2010-06-23
申请人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
发明人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
IPC分类号： G06F7/52
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.
摘要翻译：具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假定最终产品的长度为M + N个数字，并且基于该假设执行所有计算。将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。如果后者是真实的，则采用校正最终产品转换来获得适当的结果。这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。

7. 发明授权

US08131795B2 High speed adder design for a multiply-add based floating point unit 失效
标题翻译：用于基于加法的浮点单元的高速加法器设计
公开(公告)号：US08131795B2
公开(公告)日：2012-03-06
申请号：US12323257
申请日：2008-11-25
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

8. 发明申请

US20100146023A1 SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION 有权
标题翻译：具有全功能和全零检测功能
公开(公告)号：US20100146023A1
公开(公告)日：2010-06-10
申请号：US12331702
申请日：2008-12-10
申请人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
发明人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
IPC分类号： G06F7/00
CPC分类号： G06F5/01 , G06F7/02
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译：一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端，移位器。检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作，并行地移动到由最终变速级执行的换档操作以产生转换结果。

9. 发明申请

US20090077155A1 HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT 失效
标题翻译：用于基于多媒体增量浮动点单元的高速加法器设计
公开(公告)号：US20090077155A1
公开(公告)日：2009-03-19
申请号：US12323257
申请日：2008-11-25
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/50
CPC分类号： G06F7/483 , G06F7/5443
摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行终结进位功能，并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

10. 发明授权

US07461117B2 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准偏移量计算指示mo的选择信号对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。

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