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1. 发明申请

US20100146023A1 SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION 有权
标题翻译：具有全功能和全零检测功能
公开(公告)号：US20100146023A1
公开(公告)日：2010-06-10
申请号：US12331702
申请日：2008-12-10
申请人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
发明人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
IPC分类号： G06F7/00
CPC分类号： G06F5/01 , G06F7/02
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译：一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端，移位器。检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作，并行地移动到由最终变速级执行的换档操作以产生转换结果。

2. 发明授权

US08332453B2 Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result 有权
标题翻译：具有全部和全零检测的移位器，其使用部分移位向量的一部分和平移的移位量以产生移位结果
公开(公告)号：US08332453B2
公开(公告)日：2012-12-11
申请号：US12331702
申请日：2008-12-10
申请人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
发明人： Maarten Boersma , Silvia Melitta Mueller , Jochen Preiss , Holger Wetter
IPC分类号： G06F7/00
CPC分类号： G06F5/01 , G06F7/02
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译：一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端，移位器。检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作，并行地移动到由最终变速级执行的换档操作以产生转换结果。

3. 发明申请

US20100174764A1 REUSE OF ROUNDER FOR FIXED CONVERSION OF LOG INSTRUCTIONS 有权
标题翻译：固定转换日志说明的重复使用
公开(公告)号：US20100174764A1
公开(公告)日：2010-07-08
申请号：US12350680
申请日：2009-01-08
申请人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
发明人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.
摘要翻译：一种用于将有符号固定点数转换为浮点数的方法，该浮点数包括读取与要转换的有符号固定点数相对应的输入数，确定输入数是否小于零，根据输入数量小于零或大于或等于零，通过将输入数字与符号位进行异或运算来计算第一中间结果，计算第一中间结果的前导零，基于符号位填充第一中间结果，通过将填充的第一中间结果向左移动前导零来计算第二中间结果，计算指数部分和分数部分，基于符号位有条件地增加分数部分，校正指数部分和分数部分，如果递增分数部分溢出，返回浮点数。

4. 发明授权

US08626807B2 Reuse of rounder for fixed conversion of log instructions 有权
标题翻译：重复使用圆形固定转换日志指令
公开(公告)号：US08626807B2
公开(公告)日：2014-01-07
申请号：US12350680
申请日：2009-01-08
申请人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
发明人： Maarten Boersma , Markus Kaltenbach , Michael Klein , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.
摘要翻译：一种用于将有符号固定点数转换为浮点数的方法，该浮点数包括读取与要转换的有符号固定点数相对应的输入数，确定输入数是否小于零，根据输入数量小于零或大于或等于零，通过将输入数字与符号位进行异或运算来计算第一中间结果，计算第一中间结果的前导零，基于符号位填充第一中间结果，通过将填充的第一中间结果向左移动前导零来计算第二中间结果，计算指数部分和分数部分，基于符号位有条件地增加分数部分，校正指数部分和分数部分，如果递增分数部分溢出，返回浮点数。

5. 发明申请

US20100095099A1 SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS IN A REGISTER FILE 有权
标题翻译：用于在寄存器文件中存储第一和第二格式的数字的系统和方法
公开(公告)号：US20100095099A1
公开(公告)日：2010-04-15
申请号：US12250935
申请日：2008-10-14
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F9/302 , G06F9/312 , G06F7/38
CPC分类号： G06F9/30025 , G06F7/57 , G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/30192 , G06F2207/3824
摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
摘要翻译：提供了一种用于将数字存储在寄存器文件中的系统和方法。系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

6. 发明申请

US20100058266A1 3-Stack Floorplan for Floating Point Unit 有权
标题翻译：浮点单元3堆叠平面图
公开(公告)号：US20100058266A1
公开(公告)日：2010-03-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译：用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。

7. 发明授权

US08346828B2 System and method for storing numbers in first and second formats in a register file 有权
标题翻译：用于在寄存器文件中存储第一和第二格式的数字的系统和方法
公开(公告)号：US08346828B2
公开(公告)日：2013-01-01
申请号：US12250935
申请日：2008-10-14
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F5/00
CPC分类号： G06F9/30025 , G06F7/57 , G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/30192 , G06F2207/3824
摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
摘要翻译：提供了一种用于将数字存储在寄存器文件中的系统和方法。系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

8. 发明授权

US08032854B2 3-stack floorplan for floating point unit 有权
标题翻译：浮动单元的3层平面布置图
公开(公告)号：US08032854B2
公开(公告)日：2011-10-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译：用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。

9. 发明授权

US08286115B2 Fast routing of custom macros 有权
标题翻译：快速路由自定义宏
公开(公告)号：US08286115B2
公开(公告)日：2012-10-09
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

10. 发明申请

US20100146471A1 FAST ROUTING OF CUSTOM MACROS 有权
标题翻译：快速路由自定义宏
公开(公告)号：US20100146471A1
公开(公告)日：2010-06-10
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

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