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1. 发明申请

US20130173681A1 Range Check Based Lookup Tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US20130173681A1
公开(公告)日：2013-07-04
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F1/035 , G06F12/00 , G06F7/487
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路对边界单元值子集中的每个边界单元值进行第二值的比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

2. 发明授权

US08954485B2 Range check based lookup tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US08954485B2
公开(公告)日：2015-02-10
申请号：US13608189
申请日：2012-09-10
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/38 , G06F7/44
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路将第二值与边界单元值子集中的每个边界单元值进行比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

3. 发明授权

US08914431B2 Range check based lookup tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US08914431B2
公开(公告)日：2014-12-16
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路将第二值与边界单元值子集中的每个边界单元值进行比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

4. 发明申请

US20130173683A1 Range Check Based Lookup Tables 有权
公开(公告)号：US20130173683A1
公开(公告)日：2013-07-04
申请号：US13608189
申请日：2012-09-10
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/535 , G06F12/00
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

5. 发明授权

US08495124B2 Decimal floating point mechanism and process of multiplication without resultant leading zero detection 失效
标题翻译：十进制浮点机制和乘法处理，而没有得到前导零检测
公开(公告)号：US08495124B2
公开(公告)日：2013-07-23
申请号：US12821648
申请日：2010-06-23
申请人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
发明人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
IPC分类号： G06F7/52
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.
摘要翻译：具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假定最终产品的长度为M + N个数字，并且基于该假设执行所有计算。将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。如果后者是真实的，则采用校正最终产品转换来获得适当的结果。这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。

6. 发明申请

US20110320512A1 Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection 失效
标题翻译：十进制浮点机制和乘法过程，无需导致零检测
公开(公告)号：US20110320512A1
公开(公告)日：2011-12-29
申请号：US12821648
申请日：2010-06-23
申请人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
发明人： Steven R. Carlough , Adam B. Collura , Michael Kroener , Silvia Melitta Mueller
IPC分类号： G06F7/44 , G06F5/01
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.
摘要翻译：具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假设最终产品的长度为M + N个数字，并且基于该假设执行所有计算。将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。如果后者是真实的，则采用校正最终产品转换来获得适当的结果。这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。

7. 发明申请

US20110320514A1 DECIMAL ADDER WITH END AROUND CARRY 失效
标题翻译：十进制添加剂，带有附件
公开(公告)号：US20110320514A1
公开(公告)日：2011-12-29
申请号：US12822919
申请日：2010-06-24
申请人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
发明人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
IPC分类号： G06F7/485
CPC分类号： G06F7/494 , G06F7/508
摘要： Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.
摘要翻译：对于与BCD数量不同的两个BCD号码的二进制码十进制（BCD）算术加法/减法操作包括响应于BCD算术加/减操作作为减法运算，对第一个BCD运算执行BCD运算减法运算 BCD号和第二BCD号，第一BCD号具有第一幅值，第二BCD号具有第二幅值。第一幅度大于等于或小于第二幅度。执行包括：与进位生成并行，第一和第二BCD号码的部分和或部分差异是计算机，使得基于携带信息的部分和或差异可以从签名幅度形式中选择最终结果，而不进行任何后处理脚步。

8. 发明授权

US08554822B2 Decimal adder with end around carry 失效
标题翻译：十进制加法器结束周围进位
公开(公告)号：US08554822B2
公开(公告)日：2013-10-08
申请号：US12822919
申请日：2010-06-24
申请人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
发明人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
IPC分类号： G06F7/494
CPC分类号： G06F7/494 , G06F7/508
摘要： Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.
摘要翻译：对于与BCD数量不同的两个BCD号码的二进制码十进制（BCD）算术加法/减法操作包括响应于BCD算术加/减操作作为减法运算，对第一个BCD运算执行BCD运算减法运算 BCD号和第二BCD号，第一BCD号具有第一幅值，第二BCD号具有第二幅值。第一幅度大于等于或小于第二幅度。执行包括：与进位生成并行，第一和第二BCD号码的部分和或部分差异是计算机，使得基于携带信息的部分和或差异可以从签名幅度形式中选择最终结果，而不进行任何后处理脚步。

9. 发明授权

US09229722B2 Major branch instructions with transactional memory 有权
公开(公告)号：US09229722B2
公开(公告)日：2016-01-05
申请号：US13362513
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F9/46 , G06F9/38 , G06F9/32 , G06F9/52
CPC分类号： G06F9/3804 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467 , G06F9/528
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

10. 发明授权

US09021493B2 Management of resources within a computing environment 有权
公开(公告)号：US09021493B2
公开(公告)日：2015-04-28
申请号：US13615704
申请日：2012-09-14
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/46 , G06F9/38 , G06F9/50
CPC分类号： G06F9/5038 , G06F9/38 , G06F9/45533 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F9/5016 , G06F9/5077 , G06F2009/45591 , G06F2209/483 , G06F2209/5021 , G06F2209/504 , G06F2209/507 , G06F2209/508 , Y02B70/30 , Y02D10/22
摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

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