专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080148088A1 Architecture for a Physical Interface of a High Speed Front Side Bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US20080148088A1
公开(公告)日：2008-06-19
申请号：US11930345
申请日：2007-10-31
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F11/00
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

2. 发明授权

US07945805B2 Architecture for a physical interface of a high speed front side bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US07945805B2
公开(公告)日：2011-05-17
申请号：US11930345
申请日：2007-10-31
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F1/10
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

3. 发明授权

US07624297B2 Architecture for a physical interface of a high speed front side bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US07624297B2
公开(公告)日：2009-11-24
申请号：US11610063
申请日：2006-12-13
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F1/10
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：高速计算机处理器系统包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上的类似高速接口相连接的前端总线（FSB）。

4. 发明申请

US20080147952A1 Architecture for a Physical Interface of a High Speed Front Side Bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US20080147952A1
公开(公告)日：2008-06-19
申请号：US11610063
申请日：2006-12-13
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F13/36
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：高速计算机处理器系统包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

5. 发明申请

US20090193372A1 Design Structure for Improvement of Matching FET Currents Using a Digital to Analog Converter 审中-公开
标题翻译：使用数模转换器改善匹配FET电流的设计结构
公开(公告)号：US20090193372A1
公开(公告)日：2009-07-30
申请号：US12019883
申请日：2008-01-25
申请人： Steven John Baumgartner , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , H03F3/45183 , H03F3/45632 , H03F2203/45044 , H03F2203/45291
摘要： A design structure comprising apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.
摘要翻译：一种设计结构，其包括用于均衡在绝缘体上的半导体芯片上连接在一起的源的匹配的一对FET上的电流或其它FET体可被单独偏置的其他芯片的电流。在确定期间，耦合到匹配对FET的栅极的功能输入短路，并且DAC相对于第二FET的第二体电压调整匹配的一对FET中的第一FET的第一体电压在DAC的电压粒度的分辨率内，匹配的一对FET直到第一FET和第二FET中的电流相等。在从功能输入断开短路的确定周期之后，将适当的DAC控制值存储并应用于DAC。

6. 发明申请

US20090189671A1 Method and Apparatus for Improvement of Matching FET Currents Using a Digital to Analog Converter 审中-公开
标题翻译：使用数模转换器改善匹配FET电流的方法和装置
公开(公告)号：US20090189671A1
公开(公告)日：2009-07-30
申请号：US12019703
申请日：2008-01-25
申请人： Steven John Baumgartner , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06G7/18
CPC分类号： H03F3/45183 , H03F3/45632 , H03F2203/45048 , H03F2203/45342 , H03F2203/45354 , H03F2203/45438
摘要： A method and apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.
摘要翻译：一种在绝缘体上半导体芯片或其它FET体可以被单独偏置的其他芯片上，使具有连接在一起的源极的匹配的一对FET上的电流相等的方法和装置。在确定期间，耦合到匹配对FET的栅极的功能输入短路，并且DAC相对于第二FET的第二体电压调整匹配的一对FET中的第一FET的第一体电压在DAC的电压粒度的分辨率内，匹配的一对FET直到第一FET和第二FET中的电流相等。在从功能输入断开短路的确定周期之后，将适当的DAC控制值存储并应用于DAC。

7. 发明授权

US06859092B2 Method and low voltage CMOS circuit for generating voltage and current references 失效
标题翻译：用于产生电压和电流参考的方法和低压CMOS电路
公开(公告)号：US06859092B2
公开(公告)日：2005-02-22
申请号：US10418569
申请日：2003-04-17
申请人： Eric John Lukes , Patrick Lee Rosno , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , Patrick Lee Rosno , James David Strom , Dana Marie Woeste
IPC分类号： G05F1/46 , G05F1/10 , G05F3/02
CPC分类号： G05F1/46
摘要： A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.
摘要翻译：提供一种方法和低电压互补金属氧化物半导体（CMOS）电路，用于利用低电压电源产生电压和电流参考。电压产生电路提供电压参考，并由多个CMOS晶体管和电阻器形成。运算放大器包括一对差分CMOS晶体管。第一参考电压被施加到晶体管的差分对的输入和提供第二电压基准的晶体管的差分对的输出。运算放大器包括多个电流参考晶体管。第一电压产生电路产生产生第二电压的第一电压和第二电压产生电路。第一和第二电压产生电路由多个CMOS晶体管形成。产生的第一和第二电压被施加到电压参考产生电路和电流参考晶体管。

8. 发明授权

US06218901B1 High speed differential output driver with increased voltage swing and predrive common mode adjustment 有权
标题翻译：高速差分输出驱动器，具有增加的电压摆幅和预调制共模调整
公开(公告)号：US06218901B1
公开(公告)日：2001-04-17
申请号：US09415675
申请日：1999-10-12
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03F345
CPC分类号： H03F3/45179 , H03F3/3028 , H03F3/45085 , H03F3/45937 , H03F3/505 , H03F3/68 , H03F2203/45476 , H03F2203/45612 , H03F2203/45648 , H03F2203/45696 , H03K19/017563 , H03K19/018528
摘要： A high speed differential output driver is provided with increased voltage swing and predrive common mode adjustment. The high speed differential output driver includes a differential input with a voltage amplifier receiving the differential input signal and a common mode adjustment signal and providing an adjustable voltage amplified signal. An emitter follower is coupled to the voltage amplifier. The emitter follower provides a level shifted voltage amplified signal. A driver is coupled to the emitter follower receiving the level shifted voltage amplified signal and providing a driver output signal.
摘要翻译：提供高速差分输出驱动器，具有增加的电压摆幅和预调制共模调整。高速差分输出驱动器包括具有接收差分输入信号的电压放大器和共模调整信号的差分输入，并提供可调电压放大信号。射极跟随器耦合到电压放大器。射极跟随器提供电平移位电压放大信号。驱动器耦合到接收电平移位电压放大信号的发射极跟随器，并提供驱动器输出信号。

9. 发明授权

US6060939A Digitally controlled differential delay line circuit and method of controlling same 失效
标题翻译：数字控制差动延迟线电路及其控制方法
公开(公告)号：US6060939A
公开(公告)日：2000-05-09
申请号：US176140
申请日：1998-10-21
申请人： Dana Marie Woeste , James David Strom
发明人： Dana Marie Woeste , James David Strom
IPC分类号： H03H11/26 , H03K17/62
CPC分类号： H03H11/265
摘要： An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines. A reference voltage source is coupled to each of the delay elements and provides a reference voltage maintained at a substantially constant amplitude with respect to the power supply to each of the delay elements. The delayed signal may be a differential signal. Each of the delay elements may include one or more adjustable loads or adjustable current sources. An adjustable load may be implemented using P-FETs. In one embodiment, at least one of the delay elements of the first and second delay lines includes a plurality of selectable delay devices, each of which is associated with one of a plurality of selectable delay factors.
摘要翻译：一种使用可变延迟线电路来延迟信号的装置和方法。可变延迟线电路包括第一和第二延迟线，每条延迟线包括多个延迟元件。多路复用器耦合到第一和第二延迟线的相应输出，并且选择性地将第一或第二延迟线之一的输出耦合到多路复用器的输出。控制电路耦合到多路复用器和第一和第二延迟线，并且控制多路复用器，以便使用第一或第二延迟线之一在多路复用器输出端产生延迟信号，并改变另一个延迟系数的延迟因子通过改变第一或第二延迟线中的另一个的一个或多个延迟元件的电阻和电流来控制第一或第二延迟线。参考电压源耦合到每个延迟元件，并提供相对于每个延迟元件的电源维持在基本上恒定幅度的参考电压。延迟信号可以是差分信号。每个延迟元件可以包括一个或多个可调负载或可调电流源。可以使用P-FET实现可调负载。在一个实施例中，第一和第二延迟线的延迟元件中的至少一个包括多个可选择的延迟装置，每个延迟装置与多个可选择的延迟因子之一相关联。

10. 发明授权

US5903195A Automatically ranging phase locked loop circuit for microprocessor clock generation 失效
标题翻译：自动测距锁相环电路，用于微处理器时钟产生
公开(公告)号：US5903195A
公开(公告)日：1999-05-11
申请号：US16848
申请日：1998-01-30
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03L7/095 , H03L7/099 , H03L7/10 , H03L7/12
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/10 , Y10S331/02
摘要： An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control. A control signal is applied to the voltage to current converter for selectively controlling an operational mode of the voltage to current converter from a squelched operational mode to an unsquelched operational mode after a set time period. This control signal also is applied to the range control, so that the range control stops changing ranges.
摘要翻译：提供改进的锁相环（PLL）电路用于微处理器时钟产生。环形振荡器提供输出频率信号。电压 - 电流转换器将差分控制电压转换为施加到环形振荡器的可变参考电流。范围控制参考电流发生器将范围控制参考电流施加到环形振荡器。范围控制可操作地控制距离控制参考电流发生器以顺序地改变施加到环形振荡器的范围控制参考电流。耦合到量程控制的锁定检测器比较输出频率信号和参考频率信号，并且响应于比较信号将锁定信号施加到范围控制。响应于所施加的锁定信号，范围控制停止变化范围。锁相环（PLL）电路根据范围控制自动扫描多个频率子范围。控制信号被施加到电压到电流转换器，用于在设定的时间段之后选择性地将电压/电流转换器的操作模式从压缩操作模式控制到未校准的操作模式。该控制信号也适用于量程控制，使范围控制停止变化范围。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式