专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080148088A1 Architecture for a Physical Interface of a High Speed Front Side Bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US20080148088A1
公开(公告)日：2008-06-19
申请号：US11930345
申请日：2007-10-31
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F11/00
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

2. 发明授权

US07945805B2 Architecture for a physical interface of a high speed front side bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US07945805B2
公开(公告)日：2011-05-17
申请号：US11930345
申请日：2007-10-31
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F1/10
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

3. 发明授权

US07624297B2 Architecture for a physical interface of a high speed front side bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US07624297B2
公开(公告)日：2009-11-24
申请号：US11610063
申请日：2006-12-13
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F1/10
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：高速计算机处理器系统包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上的类似高速接口相连接的前端总线（FSB）。

4. 发明申请

US20080147952A1 Architecture for a Physical Interface of a High Speed Front Side Bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US20080147952A1
公开(公告)日：2008-06-19
申请号：US11610063
申请日：2006-12-13
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F13/36
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：高速计算机处理器系统包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

5. 发明申请

US20080240320A1 TRANSMIT CLOCK GENERATOR 审中-公开
标题翻译：发送时钟发生器
公开(公告)号：US20080240320A1
公开(公告)日：2008-10-02
申请号：US12135226
申请日：2008-06-09
申请人： Timothy Clyde Buchholtz
发明人： Timothy Clyde Buchholtz
IPC分类号： H04L7/00
CPC分类号： G06F1/12 , H04L7/0008 , H04L7/0091
摘要： A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a clock training period to enforce a phase relationship between the first and second divided clock signals. The synchronization signal includes at least one synchronization pulse that is applied to the first local clock generator and second local clock generator during the clock training period.
摘要翻译：发送时钟发生器包括第一本地时钟发生器和第二本地时钟发生器，每个本地时钟发生器接收外部PLL时钟信号并分别产生第一和第二分频时钟信号。在时钟训练周期期间，同步信号被施加到第一本地时钟发生器和第二本地时钟发生器，以强制第一和第二分频时钟信号之间的相位关系。同步信号包括在时钟训练周期期间施加到第一本地时钟发生器和第二本地时钟发生器的至少一个同步脉冲。

6. 发明授权

US07457387B2 Method for generating transmitter clock 失效
标题翻译：发送时钟的方法
公开(公告)号：US07457387B2
公开(公告)日：2008-11-25
申请号：US11181715
申请日：2005-07-14
申请人： Timothy Clyde Buchholtz
发明人： Timothy Clyde Buchholtz
IPC分类号： H04L7/00
CPC分类号： G06F1/12 , H04L7/0008 , H04L7/0091
摘要： A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a clock training period to enforce a phase relationship between the first and second divided clock signals. The synchronization signal includes at least one synchronization pulse that is applied to the first local clock generator and second local clock generator during the clock training period.
摘要翻译：发送时钟发生器包括第一本地时钟发生器和第二本地时钟发生器，每个本地时钟发生器接收外部PLL时钟信号并分别产生第一和第二分频时钟信号。在时钟训练周期期间，同步信号被施加到第一本地时钟发生器和第二本地时钟发生器，以强制第一和第二分频时钟信号之间的相位关系。同步信号包括在时钟训练周期期间施加到第一本地时钟发生器和第二本地时钟发生器的至少一个同步脉冲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式