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1. 发明授权

US07453293B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07453293B2
公开(公告)日：2008-11-18
申请号：US11467972
申请日：2006-08-29
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

2. 发明授权

US07420832B1 Array split across three-dimensional interconnected chips 有权
标题翻译：阵列分裂穿过三维互连芯片
公开(公告)号：US07420832B1
公开(公告)日：2008-09-02
申请号：US11741902
申请日：2007-04-30
申请人： Eric John Lukes , Nghia Van Phan
发明人： Eric John Lukes , Nghia Van Phan
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C5/063 , G11C7/12 , G11C7/18 , G11C8/14
摘要： A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.
摘要翻译：半导体存储阵列在电路的第一平面上具有第一阵列部分，在电路的第二平面上具有第二阵列部分。复合位线和/或复合字线被分割并布置成具有第一阵列部分上的第一部分和第二阵列部分上的第二部分。复合字线或复合位线的两个部分在电路的不同平面上，并且三维互连连接字线部分的近端或位线部分的近端。字线驱动器并行驱动字线部分。位线驱动器并行驱动位线部分。复合字或位线下的信号传播时间显着小于对应的未分割字或位线的信号传播时间。

3. 发明授权

US07119587B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07119587B2
公开(公告)日：2006-10-10
申请号：US10850400
申请日：2004-05-20
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.
摘要翻译：本发明提供了状态校正。从触发器接收状态电路中的第一值。接收到的值被发送到第二触发器。如果出现错误状况，则第二触发器内的接收值被改变。接收到的值被发送到第三个触发器。一方面，发送到第三触发器的接收值包括未改变的接收值。在另一方面，发送到第三触发器的接收值包括发送改变的接收值。这允许状态机中的错误状态在几个时钟脉冲之后变为正确的状态。

4. 发明授权

US06218901B1 High speed differential output driver with increased voltage swing and predrive common mode adjustment 有权
标题翻译：高速差分输出驱动器，具有增加的电压摆幅和预调制共模调整
公开(公告)号：US06218901B1
公开(公告)日：2001-04-17
申请号：US09415675
申请日：1999-10-12
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03F345
CPC分类号： H03F3/45179 , H03F3/3028 , H03F3/45085 , H03F3/45937 , H03F3/505 , H03F3/68 , H03F2203/45476 , H03F2203/45612 , H03F2203/45648 , H03F2203/45696 , H03K19/017563 , H03K19/018528
摘要： A high speed differential output driver is provided with increased voltage swing and predrive common mode adjustment. The high speed differential output driver includes a differential input with a voltage amplifier receiving the differential input signal and a common mode adjustment signal and providing an adjustable voltage amplified signal. An emitter follower is coupled to the voltage amplifier. The emitter follower provides a level shifted voltage amplified signal. A driver is coupled to the emitter follower receiving the level shifted voltage amplified signal and providing a driver output signal.
摘要翻译：提供高速差分输出驱动器，具有增加的电压摆幅和预调制共模调整。高速差分输出驱动器包括具有接收差分输入信号的电压放大器和共模调整信号的差分输入，并提供可调电压放大信号。射极跟随器耦合到电压放大器。射极跟随器提供电平移位电压放大信号。驱动器耦合到接收电平移位电压放大信号的发射极跟随器，并提供驱动器输出信号。

5. 发明授权

US06670655B2 SOI CMOS device with body to gate connection 有权
公开(公告)号：US06670655B2
公开(公告)日：2003-12-30
申请号：US09837839
申请日：2001-04-18
申请人： Eric John Lukes , Patrick Lee Rosno , James David Strom
发明人： Eric John Lukes , Patrick Lee Rosno , James David Strom
IPC分类号： H01L27148
CPC分类号： H01L27/1203 , H01L29/783
摘要： A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.

6. 发明授权

US06342793B1 Method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain 失效
标题翻译：将大量CMOS控制信号发送到单独的静音模拟电源域的方法和系统
公开(公告)号：US06342793B1
公开(公告)日：2002-01-29
申请号：US09433394
申请日：1999-11-03
申请人： Eric John Lukes , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , James David Strom , Dana Marie Woeste
IPC分类号： H03K190175
CPC分类号： H03K19/00346 , H03K19/017563
摘要： A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates. When CMOS input signal is high and Complimentary CMOS input signal is low, the pass gate comprising transistors T9 and T1 is on and transistors T8 and T0 are off and connection BSEL is pulled high turning on bipolar transistor Q9 allowing current to flow through Q9 and pulling net SB low and selecting inputs B0, B1 to be transferred to ECL Differential Outputs. Likewise, when CMOS input signal is low and Complimentary CMOS input signal is high, pass gate comprising transistors T8 and T0 is on, and transistors T9 and T1 are off, and connection ASEL is pulled high turning on bipolar transistor Q8 allowing current to flow through Q8 and pulling net SA low and selecting inputs A0, A1 to be transferred to ECL Differential Outputs.
摘要翻译： CMOS信号传输系统，用于将大量的CMOS信号发送到独立的静态模拟电源域。传输系统包括转换器子系统，其提供至少另一个器件级，CMOS信号中的噪声必须通过该器件级流动并被衰减以提供转换的CMOS信号;以及耦合到转换器的多路复用器，其中多路复用器从转换器子接收转换的CMOS信号并且还接收延迟路径控制信号。该转换器包括用于提供高电平电压基准的恒流源和恒定电流两个互补栅极，以及用于通过两个互补栅极从恒定电流源提供到地的路径的两组元件。当CMOS输入信号为高电平且免费CMOS输入信号为低电平时，包括晶体管T9和T1的通过栅导通，晶体管T8和T0断开，并连接BSEL被拉高，双极晶体管Q9导通，允许电流流过Q9并拉动净SB低，并选择输入B0，B1传输到ECL差分输出。同样地，当CMOS输入信号为低电平，并且免费CMOS输入信号为高电平时，包括晶体管T8和T0的通路导通，晶体管T9和T1截止，并且连接ASEL被拉高，导通双极晶体管Q8，允许电流流过 Q8和拉低SA SA，并选择输入A0，A1传输到ECL差分输出。

7. 发明授权

US5831484A Differential charge pump for phase locked loop circuits 失效
标题翻译：差分电荷泵用于锁相环电路
公开(公告)号：US5831484A
公开(公告)日：1998-11-03
申请号：US826436
申请日：1997-03-18
申请人： Eric John Lukes , James David Strom
发明人： Eric John Lukes , James David Strom
IPC分类号： H03L7/089
CPC分类号： H03L7/0895 , H03L7/0896
摘要： A differential charge pump is provided for use with phase locked loop (PLL) circuits including a differential loop filter and a common mode bias circuit for maintaining a predetermined bias voltage value on a high voltage filter side of the loop filter. The differential charge pump includes a reference current source. First and second current mirrors are coupled to the reference current source for providing a first mirror current and a second mirror current. A first switching transistor coupled to the first current mirror receives an input UP signal conducts current from a first side of the loop filter. A second switching transistor coupled to the second current mirror receives an input DOWN signal and conducts current from a second side of the loop filter. The first and second current mirror and switching transistors are formed by N-channel metal oxide semiconductor (NMOS) devices. The differential charge pump enables a large differential output voltage with low phase error.
摘要翻译：提供差分电荷泵用于包括差分环路滤波器和共模偏置电路的锁相环（PLL）电路，用于在环路滤波器的高电压滤波器侧上保持预定的偏置电压值。差分电荷泵包括参考电流源。第一和第二电流镜耦合到参考电流源，以提供第一反射镜电流和第二反射镜电流。耦合到第一电流镜的第一开关晶体管接收输入UP信号从环路滤波器的第一侧传导电流。耦合到第二电流镜的第二开关晶体管接收输入的DOWN信号，并且从环路滤波器的第二侧传导电流。第一和第二电流镜和开关晶体管由N沟道金属氧化物半导体（NMOS）器件形成。差分电荷泵能够实现具有低相位误差的大差分输出电压。

8. 发明申请

US20080301503A1 HIGH FREQUENCY DIVIDER STATE CORRECTION CIRCUIT 失效
标题翻译：高频分路器状态校正电路
公开(公告)号：US20080301503A1
公开(公告)日：2008-12-04
申请号：US12187517
申请日：2008-08-07
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： G06F11/28
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

9. 发明授权

US07061284B2 High frequency divider state correction circuit with data path correction 失效
标题翻译：具有数据路径校正的高分频器状态校正电路
公开(公告)号：US07061284B2
公开(公告)日：2006-06-13
申请号：US10850402
申请日：2004-05-20
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00 , H03K23/00 , H03K25/08
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled to the output of the third flip flop.
摘要翻译：本发明提供了状态校正。耦合到第二触发器的第一触发器。耦合到第二触发器的输出的状态校正电路。第三触发器耦合到状态校正电路的输出端。第四触发器耦合到第三触发器的输出。

10. 发明授权

US06973155B2 Highly scalable glitch-free frequency divider 失效
标题翻译：高度可扩展的无毛刺分频器
公开(公告)号：US06973155B2
公开(公告)日：2005-12-06
申请号：US10809592
申请日：2004-03-25
申请人： David William Boerstler , Eskinder Hailu , Eric John Lukes
发明人： David William Boerstler , Eskinder Hailu , Eric John Lukes
IPC分类号： H03K5/1252 , H03K21/00 , H03K23/66
CPC分类号： H03K23/667 , H03K5/1252
摘要： The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A frequency divider is coupled to the output of the synchronizer. A second synchronizer is coupled to the output of the comparator and the output of the frequency divider. There is feedback between the output of the second synchronizer and the enable input of the latch, the reset of the first synchronizer, the reset of the second synchronized, and the reset of the divide by n divider.
摘要翻译：本发明提供一种用于减少异常输出定时脉冲的分频器电路。锁存器耦合到分割选择线。比较器耦合到分割选择线。耦合到锁存器的输出的第一同步器。分频器耦合到同步器的输出端。第二同步器耦合到比较器的输出端和分频器的输出端。在第二同步器的输出和锁存器的使能输入之间存在反馈，第一同步器的复位，第二同步的复位以及除法的复位除以分频器。

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