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1. 发明申请

US20130329508A1 Methods And Devices For Determining Logical To Physical Mapping On An Integrated Circuit 有权
标题翻译：用于确定逻辑到物理映射的集成电路的方法和设备
公开(公告)号：US20130329508A1
公开(公告)日：2013-12-12
申请号：US13491429
申请日：2012-06-07
申请人： Stanton Petree Ashburn , Daniel L. Corum , Abha Singh Kasper , Harold C. Waite , Eric D. Rullan , Donald L. Plumton , Douglas A. Prinslow
发明人： Stanton Petree Ashburn , Daniel L. Corum , Abha Singh Kasper , Harold C. Waite , Eric D. Rullan , Donald L. Plumton , Douglas A. Prinslow
IPC分类号： G11C29/00 , H01L21/02
CPC分类号： G01R31/3172 , G01R31/2894 , G01R31/3177 , G11C29/56008 , G11C2029/1806 , G11C2029/5604 , H01L27/0207
摘要： Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.
摘要翻译：本文公开了用于将逻辑地址映射到集成电路管芯上的物理位置的方法和设备。该方法的一个实施例包括制造管芯，其中管芯具有可通过逻辑地址电接触的多个位。多个位具有在芯片上的预定位置处形成预定故障模式的已知缺陷。这些位通过使用逻辑地址进行测试，其中测试产生关于位的功能的数据。搜索测试结果的预定故障模式。基于预定故障模式的位置，构成预定故障模式的缺陷位的物理位置与其逻辑地址相关。

2. 发明授权

US09378848B2 Methods and devices for determining logical to physical mapping on an integrated circuit 有权
标题翻译：用于确定集成电路上逻辑到物理映射的方法和设备
公开(公告)号：US09378848B2
公开(公告)日：2016-06-28
申请号：US13491429
申请日：2012-06-07
申请人： Stanton Petree Ashburn , Daniel L. Corum , Abha Singh Kasper , Harold C. Waite , Eric D. Rullan , Donald L. Plumton , Douglas A. Prinslow
发明人： Stanton Petree Ashburn , Daniel L. Corum , Abha Singh Kasper , Harold C. Waite , Eric D. Rullan , Donald L. Plumton , Douglas A. Prinslow
IPC分类号： G06F11/00 , G11C29/56 , G11C29/18
CPC分类号： G01R31/3172 , G01R31/2894 , G01R31/3177 , G11C29/56008 , G11C2029/1806 , G11C2029/5604 , H01L27/0207
摘要： Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.
摘要翻译：本文公开了用于将逻辑地址映射到集成电路管芯上的物理位置的方法和设备。该方法的一个实施例包括制造管芯，其中管芯具有可通过逻辑地址电接触的多个位。多个位具有在芯片上的预定位置处形成预定故障模式的已知缺陷。这些位通过使用逻辑地址进行测试，其中测试产生关于位的功能的数据。搜索测试结果的预定故障模式。基于预定故障模式的位置，构成预定故障模式的缺陷位的物理位置与其逻辑地址相关。

3. 发明授权

US6097046A Vertical field effect transistor and diode 失效
标题翻译：垂直场效应晶体管和二极管
公开(公告)号：US6097046A
公开(公告)日：2000-08-01
申请号：US158673
申请日：1993-11-29
申请人： Donald L. Plumton
发明人： Donald L. Plumton
IPC分类号： H01L21/20 , H01L21/331 , H01L21/335 , H01L21/337 , H01L21/74 , H01L27/06 , H01L29/04 , H01L29/737 , H01L29/772 , H01L29/808 , H01L29/80 , H01L27/095
CPC分类号： H01L29/66454 , H01L21/74 , H01L27/0605 , H01L27/0629 , H01L29/045 , H01L29/66318 , H01L29/66924 , H01L29/7371 , H01L29/7722 , H01L29/8083 , H01L21/02546 , H01L21/0262 , H01L2224/0603
摘要： A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).
摘要翻译：形成在单个III-V衬底上的垂直场效应晶体管（1400）和二极管（1450）。二极管阴极和晶体管漏极或集电极可以形成在公共层（1408）中。

4. 发明授权

US5624860A Vertical field effect transistor and method 失效
标题翻译：垂直场效应晶体管及方法
公开(公告)号：US5624860A
公开(公告)日：1997-04-29
申请号：US485539
申请日：1995-06-07
申请人： Donald L. Plumton , Han-Tzong Yuan
发明人： Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L21/20 , H01L21/331 , H01L21/337 , H01L29/737 , H01L29/772 , H01L21/265 , H01L21/24 , H01L21/40
CPC分类号： H01L29/66924 , H01L21/02395 , H01L21/02433 , H01L21/02463 , H01L21/02546 , H01L21/02576 , H01L21/0262 , H01L29/66318 , H01L29/7371 , H01L29/7722
摘要： A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).
摘要翻译：垂直场效应晶体管（700）和具有掩模栅极（704）的制造方法，其具有与衬底表面相同的栅极侧壁晶体取向和低折射率衬底晶体取向，而不倾斜到更高的折射率方向。栅极（704）可以沿着沟道（706）具有调制掺杂，并且漏极（708）可以具有比可以通过栅极（704）的外延过度生长来形成沟道（704）的沟道更轻的掺杂水平 706）。

5. 发明授权

US5342795A Method of fabricating power VFET gate-refill 失效
标题翻译：制造功率VFET栅极补充的方法
公开(公告)号：US5342795A
公开(公告)日：1994-08-30
申请号：US153121
申请日：1993-11-15
申请人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
IPC分类号： H01L21/335 , H01L21/337 , H01L29/207 , H01L29/772 , H01L21/44
CPC分类号： H01L29/66454 , H01L29/207 , H01L29/66924 , H01L29/7722 , Y10S148/04
摘要： This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.
摘要翻译：这是形成垂直晶体管器件的方法，包括：形成n型第一漏极/源极层42; 图案化第一漏极/源极层42的一部分以形成沟道44和沟槽; 在沟槽中形成p型栅极结构46; 以及在栅极结构46和沟道44上形成n型第二漏极/源极层48; 接触门结构54; 与门结构56形成p欧姆接触; 形成n-欧姆源触点54; 并形成n欧姆漏极触点58.还公开了其它装置和方法。

6. 发明授权

US5223449A Method of making an integrated circuit composed of group III-V compound field effect and bipolar semiconductors 失效
标题翻译：制备由III-V族化合物场效应和双极半导体组成的集成电路的方法
公开(公告)号：US5223449A
公开(公告)日：1993-06-29
申请号：US692326
申请日：1991-04-26
申请人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
发明人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
IPC分类号： H01L27/06 , H01L27/082
CPC分类号： H01L27/0623 , H01L27/0605 , H01L27/0826 , Y10S148/009 , Y10S148/072
摘要： Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may be also be integrated on the substrate.
摘要翻译：集成电路和制造方法将NPN（192,194,210）和PNP（196,121,124）异构双极晶体管与N沟道（198,200,216,218）和P沟道（202,204,220） 222）如图1所示的单个衬底上的JFET。 MESFET也可以集成在衬底上。

7. 发明授权

US5747842A Epitaxial overgrowth method and devices 失效
标题翻译：外延过度生长法和装置
公开(公告)号：US5747842A
公开(公告)日：1998-05-05
申请号：US472791
申请日：1995-06-07
申请人： Donald L. Plumton
发明人： Donald L. Plumton
IPC分类号： H01L21/20 , H01L21/331 , H01L21/335 , H01L21/337 , H01L21/74 , H01L27/06 , H01L29/04 , H01L29/10 , H01L29/737 , H01L29/772 , H01L29/808 , H01L29/80
CPC分类号： H01L29/66454 , H01L21/74 , H01L27/0605 , H01L27/0629 , H01L29/045 , H01L29/1066 , H01L29/1075 , H01L29/66318 , H01L29/66924 , H01L29/7371 , H01L29/7722 , H01L29/8083 , H01L21/02433 , H01L21/02546 , H01L21/02576 , H01L21/02579 , H01L21/0262
摘要： A vertical field effect transistor (100) and fabrication method with buried gates; (104) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure.
摘要翻译：一种垂直场效应晶体管（100）及具有埋栅的制造方法; （104）具有间隔开的栅极指和连接结构，并且与源极和沟道外延层共同构成，随后是栅极指状物和连接结构的掺杂连接。

8. 发明授权

US5659188A Capped anneal 失效
标题翻译：封盖退火
公开(公告)号：US5659188A
公开(公告)日：1997-08-19
申请号：US475724
申请日：1995-06-07
申请人： Yung-Chung Kao , Donald L. Plumton
发明人： Yung-Chung Kao , Donald L. Plumton
IPC分类号： H01L29/73 , H01L21/20 , H01L21/203 , H01L21/324 , H01L21/331 , H01L21/338 , H01L29/205 , H01L29/737 , H01L29/812
CPC分类号： H01L21/3245 , H01L21/02381 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02631 , H01L21/02664 , Y10S148/003 , Y10S148/065 , Y10S438/902 , Y10S438/933
摘要： Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.x Ga.sub.1-x As (106), next annealing out defects with the Al.sub.x Ga.sub.1-x As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.
摘要翻译：通过首先在硅（102）上生长GaAs（104），然后生长Al x Ga 1-x As（106）的晶格匹配帽来实现晶格不匹配的半导体材料（例如硅上的GaAs）的异质外延，然后用Al x Ga 1-x As 帽（106）限制镓的解吸，最后在帽上直接生长GaAs（110）。晶格匹配盖也用作植入退火盖。

9. 发明授权

US5468661A Method of making power VFET device 失效
标题翻译：制造电源VFET器件的方法
公开(公告)号：US5468661A
公开(公告)日：1995-11-21
申请号：US78388
申请日：1993-06-17
申请人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
IPC分类号： H01L21/335 , H01L21/337 , H01L29/808 , H01L21/8258
CPC分类号： H01L29/66454 , H01L29/66924 , H01L29/8083
摘要： This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.
摘要翻译：这是形成垂直晶体管器件的方法，包括：形成n型第一漏极/源极层42; 图案化第一漏极/源极层42的一部分以形成沟道44和沟槽; 在沟槽中形成p型栅极结构46; 以及在栅极结构46和沟道44上形成n型第二漏极/源极层48.还公开了其它器件和方法。

10. 发明授权

US5369042A Enhanced performance bipolar transistor process 失效
标题翻译：增强性能双极晶体管工艺
公开(公告)号：US5369042A
公开(公告)日：1994-11-29
申请号：US26886
申请日：1993-03-05
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L21/331 , H01L27/06 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
摘要翻译：这是一种形成双极晶体管的方法，包括：在衬底上形成具有掺杂类型和掺杂水平的子集电极层; 在子集电极层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第一层; 增加第一层的第一和第二区域的掺杂水平; 在第一层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第二层; 增加在第一层的第一区域之上的第二层的第一区域的掺杂水平，由此子集电极层，第一层的第一区域和第二层的第一区域是晶体管的集电极; 在与所述子集电极层相反的掺杂类型的第二层上形成基底层; 并且在基底层上形成与子集电极层相同的掺杂类型的发射极层。还公开了其它装置和方法。

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