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1. 发明授权

US5335219A Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements 失效
标题翻译：微晶半导体材料，半导体器件和由其制造的直接可重写存储元件的均匀组成，以及由存储元件制造的阵列
公开(公告)号：US5335219A
公开(公告)日：1994-08-02
申请号：US768139
申请日：1991-09-30
申请人： Stanford R. Ovshinsky , Stephen J. Hudgens , David A. Strand , Wolodymyr Czubatyj , Jesus Gonzalez-Hernandez , Hellmut Fritzsche , Qiuyi Ye , Sergey A. Kostylev , Benjamin S. Chao
发明人： Stanford R. Ovshinsky , Stephen J. Hudgens , David A. Strand , Wolodymyr Czubatyj , Jesus Gonzalez-Hernandez , Hellmut Fritzsche , Qiuyi Ye , Sergey A. Kostylev , Benjamin S. Chao
IPC分类号： H01L27/10 , G11C11/56 , G11C16/02 , H01H45/00 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L27/24 , H01L29/788 , H01L29/792 , H01L45/00 , G11C13/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , H01L27/115 , G11C13/04
摘要： A unique class of microcrystalline semiconductor materials which can be modulated, within a crystalline phase, to assume any one of a large dynamic range of different Fermi level positions while maintaining a substantially constant band gap over the entire range, even after a modulating field has been removed. A solid state, directly overwritable, electronic and optical, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory based upon the novel switching characteristics provided by said unique class of semiconductor materials, which memory exhibits orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory of the instant invention is in turn characterized, inter alia, by numerous stable and non-volatile detectable configurations of local atomic order, which configurations can be selectively and repeatably accessed by input signals of varying levels.
摘要翻译：一种独特的微晶半导体材料，其可以在晶相内被调制以承担不同费米能级位置的大动态范围中的任何一种，同时在整个范围内保持基本恒定的带隙，即使在调制场已经被删除。基于由所述独特类型的半导体材料提供的新型开关特性的固态，直接可重写的，电子和光学，非易失性，高密度，低成本，低能量，高速度，容易制造的多单元单元存储器，其中存储器在显着降低的能量水平下显示出高数量级的开关速度。特别地，本发明的新颖记忆特征还在于本地原子序列的许多稳定和非易失性可检测配置，其可通过不同等级的输入信号选择性地和可重复地访问这些配置。

2. 发明授权

US5406509A Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom 失效
标题翻译：电可擦除的直接可重写的多单元单元存储元件和由其制造的阵列
公开(公告)号：US5406509A
公开(公告)日：1995-04-11
申请号：US46249
申请日：1993-04-12
申请人： Stanford R. Ovshinsky , Qiuyi Ye , David A. Strand , Wolodymyr Czubatyj
发明人： Stanford R. Ovshinsky , Qiuyi Ye , David A. Strand , Wolodymyr Czubatyj
IPC分类号： G11C11/56 , G11C16/02 , H01L27/24 , H01L45/00 , G11C17/14
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/144 , G11C13/04 , G11C2213/72
摘要： The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of electrical resistance values; and (2) the ability to be set at one of a plurality of resistance values within said dynamic range in response to selected electrical input signals so as to provide said single cell with multibit storage capabilities. The memory element also includes a pair of spacedly disposed contacts for supplying the electrical input signal to set the memory material to a selected resistance value within the dynamic range. At least a filamentary portion of the single cell memory element being setable, by the selected electrical signal to any resistance value in said dynamic range, regardless of the previous resistance value of said material. The memory element further includes a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed contacts. The controlling means defining the size and position of the filamentary portion during electrical formation of the memory element and limiting the size and confining the location of the filamentary portion during use of the memory element, thereby providing for a high current density within the filamentary portion of the single cell memory element upon input of a very low total current electrical signal to the spacedly disposed contacts.
摘要翻译：本发明包括电操作的直接覆盖的多位单个单元存储元件。存储元件包括限定单个单元存储元件的一定量的存储器材料。记忆材料的特征在于：（1）电阻值的大动态范围; 以及（2）响应于所选择的电输入信号在所述动态范围内被设置为多个电阻值之一的能力，以便向所述单个单元提供多位存储能力。存储元件还包括一对间隔设置的触点，用于提供电输入信号以将存储器材料设置在动态范围内的所选电阻值。所述单个单元存储元件的至少一个细长部分可被所选择的电信号设定到所述动态范围内的任何电阻值，而与所述材料的先前电阻值无关。存储元件还包括设置在存储器材料体积与间隔设置的触点中的至少一个之间的丝状部分控制装置。控制装置在存储元件的电气形成期间限定丝状部分的尺寸和位置，并且在存储元件的使用期间限制尺寸并限制丝状部分的位置，由此提供丝网部分内的高电流密度当输入非常低的总电流电信号到间隔布置的触点时，单个单元存储元件。

3. 发明授权

US07561483B2 Internally asymmetric method for evaluating static memory cell dynamic stability 失效
标题翻译：用于评估静态存储单元动态稳定性的内部非对称方法
公开(公告)号：US07561483B2
公开(公告)日：2009-07-14
申请号：US11685904
申请日：2007-03-14
申请人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/006 , G11C29/12005 , G11C29/24 , G11C2029/5002
摘要： An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
摘要翻译：用于评估静态存储单元动态稳定性的内部非对称方法提供了一种提高存储器阵列的性能超越现有水平/产量的机制。通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。或者或组合地，可以改变单元的输出处的负载以影响电池的性能。可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

4. 发明申请

US20070165471A1 INTERNALLY ASYMMETRIC METHOD FOR EVALUATING STATIC MEMORY CELL DYNAMIC STABILITY 失效
标题翻译：用于评估静态存储单元动态稳定性的内部非对称方法
公开(公告)号：US20070165471A1
公开(公告)日：2007-07-19
申请号：US11685904
申请日：2007-03-14
申请人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/006 , G11C29/12005 , G11C29/24 , G11C2029/5002
摘要： An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
摘要翻译：用于评估静态存储单元动态稳定性的内部非对称方法提供了一种提高存储器阵列的性能超越现有水平/产量的机制。通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。或者或组合地，可以改变单元的输出处的负载以影响电池的性能。可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

5. 发明授权

US07558136B2 Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability 有权
标题翻译：用于评估静态存储单元动态稳定性的内部非对称方法和电路
公开(公告)号：US07558136B2
公开(公告)日：2009-07-07
申请号：US11838341
申请日：2007-08-14
申请人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv V. Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/006 , G11C29/12005 , G11C29/24 , G11C2029/5002
摘要： A memory cell having an asymmetric connection for evaluating dynamic stability provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By operating the cell and observing changes in performance caused by the asymmetry, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each crosscoupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
摘要翻译：具有用于评估动态稳定性的不对称连接的存储器单元提供了一种用于提高存储器阵列的性能超过当前水平/产量的机制。通过操作电池并观察由不对称引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。或者或组合地，可以改变单元的输出处的负载以影响电池的性能。可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

6. 发明申请

US20070086232A1 Ring oscillator row circuit for evaluating memory cell performance 有权
标题翻译：用于评估存储单元性能的环形振荡器行电路
公开(公告)号：US20070086232A1
公开(公告)日：2007-04-19
申请号：US11250019
申请日：2005-10-13
申请人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
摘要翻译：用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

7. 发明申请

US20070058448A1 Bitline variable methods and circuits for evaluating static memory cell dynamic stability 失效
公开(公告)号：US20070058448A1
公开(公告)日：2007-03-15
申请号：US11225571
申请日：2005-09-13
申请人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C11/41 , G11C29/006 , G11C29/50 , G11C2029/1204 , G11C2029/5002
摘要： Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.

8. 发明授权

US06528855B2 MOSFET having a low aspect ratio between the gate and the source/drain 失效
标题翻译： MOSFET在栅极和源极/漏极之间具有低的纵横比
公开(公告)号：US06528855B2
公开(公告)日：2003-03-04
申请号：US09911894
申请日：2001-07-24
申请人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
发明人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
IPC分类号： H01L29772
CPC分类号： H01L29/0653 , H01L21/823814 , H01L21/823878 , H01L29/66621 , H01L29/66636 , H01L29/7834
摘要： A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.
摘要翻译：具有新的源极/漏极（S / D）结构的MOSFET特别适用于现代CMOS技术的较小特征尺寸。 S / D导体位于浅沟槽隔离（STI）上，以实现低结漏电和低结电容。通过STI蚀刻步骤（根据制造MOSFET的第一种方法）或硅蚀刻步骤（根据制造MOSFET的第二种方法）限定S / D结深度。通过控制蚀刻深度，实现非常浅的结深度。栅极长度的变化很小，因为栅极区域是通过蚀刻晶体硅来定义的，而不是蚀刻多晶硅。由于栅极导体和源极和漏极导体在同一个电平上对齐，栅极和S / D之间的纵横比较低。自杀技术应用于源极和漏极，用于低寄生电阻; 然而，这不会导致严重的S / D结泄漏，因为源极和漏极导体位于STI上。

9. 发明申请

US20080094878A1 RING OSCILLATOR ROW CIRCUIT FOR EVALUATING MEMORY CELL PERFORMANCE 失效
标题翻译：用于评估存储器单元性能的振荡器振荡器电路
公开(公告)号：US20080094878A1
公开(公告)日：2008-04-24
申请号：US11963794
申请日：2007-12-22
申请人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
摘要翻译：用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

10. 发明申请

US20050199966A1 Dual work function semiconductor structure with borderless contact and method of fabricating the same 失效
标题翻译：具有无边界接触的双功能半导体结构及其制造方法
公开(公告)号：US20050199966A1
公开(公告)日：2005-09-15
申请号：US11098103
申请日：2005-04-04
申请人： Qiuyi Ye , William Tonti , Yujun Li
发明人： Qiuyi Ye , William Tonti , Yujun Li
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
摘要翻译：提出了一种具有无边界接触的双功能半导体结构及其制造方法。该结构可以包括具有基本无帽栅极的场效应晶体管（FET）和与无盖栅极相邻的扩散部的导电接触，其中导电触点与栅极无边界。由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。

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