专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050138329A1 Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects 失效
标题翻译：基于垃圾回收器分析和对象布局动态插入预取指令的方法和装置
公开(公告)号：US20050138329A1
公开(公告)日：2005-06-23
申请号：US10741897
申请日：2003-12-19
申请人： Sreenivas Subramoney , Mauricio Serrano , Richard Hudson , Ali-Reza Adl-Tabatabai
发明人： Sreenivas Subramoney , Mauricio Serrano , Richard Hudson , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45 , G06F12/02 , G06F15/00
CPC分类号： G06F12/0253 , G06F12/0862 , G06F2212/6026
摘要： Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring unit in a processor system. Based on sample information associated with the one or more samples, delinquent information is generated. To dynamically insert one or more prefetch instructions, a prefetch point is identified based on the delinquent information.
摘要翻译：公开了动态插入预取指令的方法和装置。在示例性方法中，与处理器系统中的性能监视单元识别与高速缓存未命中相关联的一个或多个样本。根据与一个或多个样本相关联的样本信息，生成违法信息。为了动态地插入一个或多个预取指令，基于拖欠信息来识别预取点。

2. 发明授权

US07490117B2 Dynamic performance monitoring-based approach to memory management 失效
标题翻译：基于动态性能监控的内存管理方法
公开(公告)号：US07490117B2
公开(公告)日：2009-02-10
申请号：US10749425
申请日：2003-12-31
申请人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
发明人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/08
CPC分类号： G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
摘要： Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.
摘要翻译：描述了用于优化处理器系统中的存储器管理的技术。这些技术可以在包括片上性能监视的处理器以及外部性能监视器耦合到处理器的系统上实现。包括性能监控单元（PMU）的处理器就是例子。 PMU可以将数据存储在读取和写入高速缓存未命中，以及翻译后备缓冲区（TLB）未命中的数据。来自PMU的数据用于确定存储器堆中的任何存储器区域是否是过期存储器区域，即表现出大量存储器问题或失速的区域。如果发现存在不正当的内存区域，诸如垃圾收集例程的存储器管理器可以通过改进堆中对象的布局来有效地优化存储器性能以及突变器的性能。以这种方式，可以基于动态和实时存储器性能数据来集中存储器管理例程。

3. 发明申请

US20060143421A1 Dynamic performance monitoring-based approach to memory management 失效
公开(公告)号：US20060143421A1
公开(公告)日：2006-06-29
申请号：US10749425
申请日：2003-12-31
申请人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
发明人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00
CPC分类号： G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
摘要： Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.

4. 发明申请

US20050138294A1 Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis 失效
标题翻译：基于编译器和垃圾回收器分析动态插入预取指令的方法和装置
公开(公告)号：US20050138294A1
公开(公告)日：2005-06-23
申请号：US10742009
申请日：2003-12-19
申请人： Mauricio Serrano , Sreenivas Subramoney , Richard Hudson , Ali-Reza Adl-Tabatabai
发明人： Mauricio Serrano , Sreenivas Subramoney , Richard Hudson , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45 , G06F12/02 , G06F12/00
CPC分类号： G06F12/0253
摘要： Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.
摘要翻译：公开了基于垃圾收集器分析和编译器分析来插入预取指令的方法和装置。在示例性方法中，接收与处理器系统中的来自性能监视单元的高速缓存未命中关联的一个或多个批次的样本。选择一个或多个基于犯罪信息的样本的一个或多个样本。产生与一个或多个样本相关联的性能影响指示符。基于性能指标，启动垃圾回收器分析和编译器分析中的至少一个以识别一个或多个违规路径。基于垃圾收集器分析和编译器分析中的至少一个，识别插入预取指令的一个或多个预取点。

5. 发明申请

US20050120337A1 Memory trace buffer 审中-公开
标题翻译：内存跟踪缓冲区
公开(公告)号：US20050120337A1
公开(公告)日：2005-06-02
申请号：US10725730
申请日：2003-12-01
申请人： Mauricio Serrano , Ali-Reza Adl-Tabatabai , Anwar Ghuloum , Dong-Yuan Chen , Richard Hudson
发明人： Mauricio Serrano , Ali-Reza Adl-Tabatabai , Anwar Ghuloum , Dong-Yuan Chen , Richard Hudson
IPC分类号： G06F9/44
CPC分类号： G06F11/28
摘要： According to an embodiment of the invention, a method and apparatus are described for memory trace buffering. An embodiment of a processor includes an execution unit and a buffer. The buffer is to store certain data regarding each memory operation of a plurality of memory operations that are executed by the processor.
摘要翻译：根据本发明的实施例，描述了一种用于存储器跟踪缓冲的方法和装置。处理器的实施例包括执行单元和缓冲器。缓冲器用于存储关于由处理器执行的多个存储器操作的每个存储器操作的某些数据。

6. 发明授权

US07577947B2 Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects 失效
标题翻译：基于垃圾回收器分析和对象布局动态插入预取指令的方法和装置
公开(公告)号：US07577947B2
公开(公告)日：2009-08-18
申请号：US10741897
申请日：2003-12-19
申请人： Sreenivas Subramoney , Mauricio J. Serrano , Richard L. Hudson , Ali-Reza Adl-Tabatabai
发明人： Sreenivas Subramoney , Mauricio J. Serrano , Richard L. Hudson , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45
CPC分类号： G06F12/0253 , G06F12/0862 , G06F2212/6026
摘要： Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring unit in a processor system. Based on sample information associated with the one or more samples, delinquent information is generated. To dynamically insert one or more prefetch instructions, a prefetch point is identified based on the delinquent information.
摘要翻译：公开了动态插入预取指令的方法和装置。在示例性方法中，与处理器系统中的性能监视单元识别与高速缓存未命中相关联的一个或多个样本。根据与一个或多个样本相关联的样本信息，生成违法信息。为了动态地插入一个或多个预取指令，基于拖欠信息来识别预取点。

7. 发明授权

US07389385B2 Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis 失效
标题翻译：基于编译器和垃圾回收器分析动态插入预取指令的方法和装置
公开(公告)号：US07389385B2
公开(公告)日：2008-06-17
申请号：US10742009
申请日：2003-12-19
申请人： Mauricio J. Serrano , Sreenivas Subramoney , Richard L. Hudson , Ali-Reza Adl-Tabatabai
发明人： Mauricio J. Serrano , Sreenivas Subramoney , Richard L. Hudson , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00 , G06F9/26 , G06F9/45 , G06F11/30
CPC分类号： G06F12/0253
摘要： Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.
摘要翻译：公开了基于垃圾收集器分析和编译器分析来插入预取指令的方法和装置。在示例性方法中，接收与处理器系统中的来自性能监视单元的高速缓存未命中关联的一个或多个批次的样本。选择一个或多个基于犯罪信息的样本的一个或多个样本。产生与一个或多个样本相关联的性能影响指示符。基于性能指标，启动垃圾回收器分析和编译器分析中的至少一个以识别一个或多个违规路径。基于垃圾收集器分析和编译器分析中的至少一个，识别插入预取指令的一个或多个预取点。

8. 发明申请

US20150040111A1 HANDLING PRECOMPILED BINARIES IN A HARDWARE ACCELERATED SOFTWARE TRANSACTIONAL MEMORY SYSTEM 有权
标题翻译：在硬件加速软件交易存储系统中处理预先确定的二进制
公开(公告)号：US20150040111A1
公开(公告)日：2015-02-05
申请号：US14271024
申请日：2014-05-06
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn A. Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn A. Jacobson
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F12/08
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/467 , G06F12/0837 , G06F2212/62
摘要： A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries. Furthermore, new versions of newly compiled functions may be inserted to provide strong atomicity between previously and newly compiled functions.
摘要翻译：这里描述了使用预编译二进制文件实现软件事务存储器（STM）的方法和装置。在事务中遇到访问操作时，检查与由访问引用的存储器位置相关联的注释字段。响应于表示事务内先前类似访问的存储器位置，访问被执行而没有访问障碍。然而，如果注释字段处于表示在事务的挂起期间没有先前访问的默认状态，则确定处理器的模式。如果处理器模式处于隐式模式，则异步执行访问处理程序/障碍。相反，在显式模式下，设置标志而不是异步执行处理程序。此外，在编译期间，转换显式和转换隐式指令将被智能地转换为预编译和新编译的二进制文件的模式。此外，可以插入新版本的新编译的函数，以便在先前和新编译的函数之间提供强大的原子性。

9. 发明授权

US08949777B2 Methods and systems for mapping a function pointer to the device code 有权
标题翻译：将功能指针映射到设备代码的方法和系统
公开(公告)号：US08949777B2
公开(公告)日：2015-02-03
申请号：US13092500
申请日：2011-04-22
申请人： Yang Ni , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman
发明人： Yang Ni , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/52
摘要： Methods for mapping a function pointer to the device code are presented. In one embodiment, a method includes identifying a function which is executable by processing devices. The method includes generating codes including a first code corresponds to a first processing device and a second code corresponds to a second processing device. The second processing device is architecturally different from the first processing device. The method further includes storing the second code in a byte string such that the second code is retrievable if the function will be executed by the second processing device.
摘要翻译：介绍了将功能指针映射到设备代码的方法。在一个实施例中，一种方法包括识别可由处理设备执行的功能。该方法包括生成代码，其包括对应于第一处理设备的第一代码，第二代码对应于第二处理设备。第二处理装置在结构上与第一处理装置不同。该方法还包括将第二代码存储在字节串中，使得如果功能将被第二处理设备执行，则可检索第二代码。

10. 发明授权

US08719514B2 Software filtering in a transactional memory system 有权
标题翻译：事务存储系统中的软件过滤
公开(公告)号：US08719514B2
公开(公告)日：2014-05-06
申请号：US12653471
申请日：2009-12-15
申请人： Ali-Reza Adl-Tabatabai , David Callahan , Jan Gray , Vinod Grover , Bratin Saha , Gad Sheaffer
发明人： Ali-Reza Adl-Tabatabai , David Callahan , Jan Gray , Vinod Grover , Bratin Saha , Gad Sheaffer
IPC分类号： G06F13/00
CPC分类号： G06F9/522 , G06F8/458 , G06F9/467
摘要： A method and apparatus for utilizing hardware mechanisms of a transactional memory system is herein described. Various embodiments relate to software-based filtering of operations from read and write barriers and read isolation barriers during transactional execution. Other embodiments relate to software-implemented read barrier processing to accelerate strong atomicity. Other embodiments are also described and claimed.
摘要翻译：这里描述了一种利用事务存储器系统的硬件机制的方法和装置。各种实施例涉及在事务执行期间从读写障碍和读隔离屏障的基于软件的操作过滤。其他实施例涉及软件实现的读屏障处理以加速强原子性。还描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式